ATTINY43U-MU Atmel, ATTINY43U-MU Datasheet - Page 135

• Manufacturer Part Number: ATTINY43U-MU
• Description: MCU AVR 4K FLASH 8MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY43U-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• For Use With: ATSTK600-TINYX3U - STK600 SOCKET/ADAPTER TINYX3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.5
18.6
18.6.1
18.6.2
8048B–AVR–03/09
EEPROM Write Prevents Writing to SPMCSR
Reading the Fuse and Lock Bits from Software
Reading Lock Bits from Firmware
Reading Fuse Bits from Firmware
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
It is possible for firmware to read device fuse and lock bits. In addition, firmware can also read
data from the device signature imprint table (see
Note:
Lock bit values are returned in the destination register after an LPM instruction has been issued
within three CPU cycles after RFLB and SPMEN bits have been set in SPMCSR. The RFLB and
SPMEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction
is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.
When RFLB and SPMEN are cleared LPM functions normally.
To read the lock bits, follow the below procedure:
If successful, the contents of the destination register are as follows.
See section
The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,
only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:
If successful, the contents of the destination register are as follows.
Refer to
Bit
Rd
Bit
Rd
1. Load the Z-pointer with 0x0001.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the lock bits from the LPM destination register.
1. Load the Z-pointer with 0x0000.
2. Set RFLB and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Read the FLB from the LPM destination register.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-
grammed, will be read as one.
Table 19-5 on page 141
“Program And Data Memory Lock Bits” on page 139
FLB7
7
–
7
FLB6
6
–
6
for a detailed description and mapping of the Fuse Low Byte.
FLB5
5
–
5
FLB4
4
–
4
page
FLB3
3
–
3
141).
FLB2
2
–
2
for more information.
FLB1
LB2
1
1
FLB0
LB1
0
0
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