DF2398F20V Renesas Electronics America, DF2398F20V Datasheet
DF2398F20V
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DF2398F20V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2357 Group, H8S/2357F-ZTAT 16 H8S/2398F-ZTAT Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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This LSI is a single-chip microcomputer with a 32-bit H8S/2000 CPU core, and a set of on-chip peripheral functions required for system configuration. This LSI is equipped with ROM, RAM, a bus controller, a data transfer controller (DTC), a programmable ...
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User's manuals for development tools: Manual Title H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual H8S, H8/300 Series High-performance Embedded Workshop User's Manual Application Note: Manual Title H8S Family ...
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Main Revisions for This Edition 1.1 Overview Table 1-1 Overview 4.1.3 Exception Vector Table 6.6.1 When DDS = 1 Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access) 6.6.2 When DDS = ...
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9.8.2 Register Configuration 9.9.2 Register Configuration (On- Chip ROM Version Only) 9.10.2 Register Configuration (On- Chip ROM Version Only) 9.11.2 Register Configuration (On- Chip ROM Version Only) Rev.6.00 Oct.28.2004 page iv of xxiv REJ09B0138-0600H P a ...
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9.12.2 Register Configuration 10.4.5 Cascaded Operation Figure10-23 Example of Cascaded Operation (2) 10.7 Usage Note Figure 10-57 Contention between TCNT Write and Overflow 11.3.1 Overview Figure 11-2 PPG Output Operation 14.2.8 Bit Rate Register (BRR) Table ...
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19.18.2 Program-Verify Mode Figure 19-48 Program/Program- Verify Flowchart 22.3.6 Flash Memory Characteristics Table 22-21 Flash Memory Characteristics (HD64F2398F20, HD64F2398TE20) Table 22-22 Flash Memory Characteristics (HD64F2398F20T, HD64F2398TE20T) Rev.6.00 Oct.28.2004 page vi of xxiv REJ09B0138-0600H ...
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A.5 Bus States during Instruction Execution Table A-6 Instruction Execution Cycles Revision (See Manual for Details) 827 Table A-6 amended Rev.6.00 Oct.28.2004 page vii of xxiv REJ09B0138-0600H ...
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Product Code Lineup Table G-2 H8S/2398, H8S/2394, H8S/2392, H8S/2390 Group Product Code Lineup H. Package Dimensions Figure H-1 TFP-120 Package Dimension Rev.6.00 Oct.28.2004 page viii of xxiv REJ09B0138-0600H Revision (See Manual ...
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Section 1 Overview...............................................................................................................................1 1.1 Overview....................................................................................................................................................................... 1 1.2 Block Diagram..............................................................................................................................................................6 1.3 Pin Description ............................................................................................................................................................. 7 1.3.1 Pin Arrangement ............................................................................................................................................. 7 1.3.2 Pin Functions in Each Operating Mode......................................................................................................... 11 1.3.3 Pin Functions................................................................................................................................................. 15 Section 2 CPU.....................................................................................................................................21 2.1 Overview..................................................................................................................................................................... 21 2.1.1 Features ......................................................................................................................................................... ...
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Section 3 MCU Operating Modes ......................................................................................................55 3.1 Overview..................................................................................................................................................................... 55 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) ................................................................................. 55 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) ............... 56 3.1.3 Register Configuration ..................................................................................................................................57 3.2 Register Descriptions..................................................................................................................................................57 3.2.1 ...
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Interrupt Priority Registers (IPRA to IPRK) ..................................................................................... 84 5.2.3 IRQ Enable Register (IER) ........................................................................................................................... 85 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..............................................................................86 5.2.5 IRQ Status Register (ISR) ............................................................................................................................. 86 5.3 Interrupt Sources......................................................................................................................................................... 87 ...
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Wait Control ................................................................................................................................................136 6.5 DRAM Interface....................................................................................................................................................... 138 6.5.1 Overview ..................................................................................................................................................... 138 6.5.2 Setting DRAM Space ..................................................................................................................................138 6.5.3 Address Multiplexing ..................................................................................................................................138 6.5.4 Data Bus ......................................................................................................................................................138 6.5.5 Pins Used for DRAM Interface ................................................................................................................... 139 6.5.6 Basic Timing ............................................................................................................................................... 140 6.5.7 Precharge ...
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Memory Address Register (MAR) ..............................................................................................................181 7.3.2 I/O Address Register (IOAR)......................................................................................................................181 7.3.3 Execute Transfer Count Register (ETCR)................................................................................................... 181 7.3.4 DMA Control Register (DMACR)..............................................................................................................183 7.3.5 DMA Band Control Register (DMABCR)..................................................................................................186 7.4 Register Descriptions (3) ..........................................................................................................................................190 7.4.1 DMA Write Enable Register (DMAWER) ...
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Block Transfer Mode................................................................................................................................... 258 8.3.8 Chain Transfer............................................................................................................................................. 259 8.3.9 Operation Timing ........................................................................................................................................260 8.3.10 Number of DTC Execution States............................................................................................................... 261 8.3.11 Procedures for Using DTC ..........................................................................................................................262 8.3.12 Examples of Use of the D7TC..................................................................................................................... 262 8.4 Interrupts................................................................................................................................................................... 264 8.5 Usage Notes ...
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Register Configuration (On-Chip ROM Version Only)..............................................................................318 9.11.3 Pin Functions............................................................................................................................................... 320 9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)....................................................................321 9.12 Port E ........................................................................................................................................................................322 9.12.1 Overview ..................................................................................................................................................... 322 9.12.2 Register Configuration ................................................................................................................................323 9.12.3 Pin Functions............................................................................................................................................... 325 9.12.4 MOS Input Pull-Up ...
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Usage Notes ..............................................................................................................................................................404 Section 11 Programmable Pulse Generator (PPG) ...........................................................................411 11.1 Overview................................................................................................................................................................... 411 11.1.1 Features ....................................................................................................................................................... 411 11.1.2 Block Diagram............................................................................................................................................. 412 11.1.3 Pin Configuration ........................................................................................................................................413 11.1.4 Registers ......................................................................................................................................................414 11.2 Register Descriptions................................................................................................................................................415 11.2.1 Next Data Enable Registers H and L ...
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Contention between TCNT Write and Increment ....................................................................................... 449 12.6.3 Contention between TCOR Write and Compare Match ............................................................................. 450 12.6.4 Contention between Compare Matches A and B ........................................................................................450 12.6.5 Switching of Internal Clocks and TCNT Operation................................................................................... 451 12.6.6 Interrupts and ...
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SCI Interrupts ........................................................................................................................................................... 512 14.5 Usage Notes ..............................................................................................................................................................514 Section 15 Smart Card Interface.......................................................................................................517 15.1 Overview................................................................................................................................................................... 517 15.1.1 Features ....................................................................................................................................................... 517 15.1.2 Block Diagram............................................................................................................................................. 518 15.1.3 Pin Configuration ........................................................................................................................................518 15.1.4 Register Configuration ................................................................................................................................519 15.2 Register Descriptions................................................................................................................................................520 15.2.1 Smart Card Mode ...
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D/A Control Register (DACR)....................................................................................................................557 17.2.3 Module Stop Control Register (MSTPCR) ................................................................................................. 558 17.3 Operation ..................................................................................................................................................................559 Section 18 RAM................................................................................................................................561 18.1 Overview................................................................................................................................................................... 561 18.1.1 Block Diagram ............................................................................................................................................561 18.1.2 Register Configuration ................................................................................................................................561 18.2 Register Descriptions................................................................................................................................................562 18.2.1 System Control Register (SYSCR) ............................................................................................................. 562 ...
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Error Protection ........................................................................................................................................... 599 19.11 Flash Memory Emulation in RAM........................................................................................................................... 601 19.11.1 Emulation in RAM ......................................................................................................................................601 19.11.2 RAM Overlap ..............................................................................................................................................602 19.12 Interrupt Handling when Programming/Erasing Flash Memory ..............................................................................603 19.13 Flash Memory Programmer Mode ........................................................................................................................... 604 19.13.1 Programmer Mode Setting ...
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Socket Adapters and Memory Map............................................................................................................. 648 19.22.3 Programmer Mode Operation......................................................................................................................650 19.22.4 Memory Read Mode....................................................................................................................................651 19.22.5 Auto-Program Mode ................................................................................................................................... 653 19.22.6 Auto-Erase Mode......................................................................................................................................... 655 19.22.7 Status Read Mode........................................................................................................................................656 19.22.8 Status Polling............................................................................................................................................... 657 19.22.9 Programmer Mode Transition Time............................................................................................................657 19.22.10 Notes on ...
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AC Characteristics....................................................................................................................................... 684 22.1.4 A/D Conversion Characteristics ..................................................................................................................701 22.1.5 D/A Conversion Characteristics ..................................................................................................................702 22.2 Usage Note (Internal Voltage Step Down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390) ................... 702 22.3 Electrical Characteristics of H8S/2398 F-ZTAT......................................................................................................703 22.3.1 Absolute Maximum Ratings........................................................................................................................703 ...
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C.12 Port F Block Diagram............................................................................................................................................... 996 C.13 Port G Block Diagram ............................................................................................................................................1004 Appendix D Pin States ....................................................................................................................1007 D.1 Port States in Each Mode ....................................................................................................................................... 1007 Appendix E Pin States at Power-On ...............................................................................................1011 E.1 When Pins Settle from an Indeterminate State ...
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Rev.6.00 Oct.28.2004 page xxiv of xxiv REJ09B0138-0600H ...
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Overview The H8S/2357 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen ...
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Table 1-1 Overview Item CPU Bus controller DMA controller (DMAC) Data transfer controller (DTC) Rev.6.00 Oct.28.2004 page 2 of 1016 REJ09B0138-0600H Specification General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation ...
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Item Specification 6-channel 16-bit timer on-chip 16-bit timer-pulse unit (TPU) Pulse I/O processing capability for pins Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Programmable pulse generator Output trigger selectable ...
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Item Interrupt controller Power-down state Operating modes Rev.6.00 Oct.28.2004 page 4 of 1016 REJ09B0138-0600H Specification Nine external interrupt pins (NMI, IRQ0 to IRQ7) 52 internal interrupt sources Eight priority levels settable Medium-speed mode Sleep mode Module stop mode Software standby ...
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Item Specification Four MCU operating modes (H8S/2398 F-ZTAT, masked ROM, ROMless, and Operating modes ZTAT) CPU Operating Mode Mode 0 — Advanced Notes the H8S/2398 F-ZTAT, modes ...
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Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2357 Group EXTAL XTAL STBY RES WDTOVF (FWE NMI PF / ø ...
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Pin Description 1.3.1 Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement for the H8S/2357, H8S/2352 and figures 1-4 and 1-5 show the pin arrangements for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. SCK2 / P5 2 ADTRG / ...
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AV 103 CC V 104 ref AN0 / P4 105 0 AN1 / P4 106 1 AN2 / P4 107 2 AN3 / P4 108 3 AN4 / P4 109 4 AN5 / P4 110 5 DA0 / AN6 / ...
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SCK2 / ADTRG / ref AN0 / AN1 / AN2 / AN3 / AN4 / P4 99 ...
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AV 103 CC V 104 ref AN0 / P4 105 0 AN1 / P4 106 1 AN2 / P4 107 2 AN3 / P4 108 3 AN4 / P4 109 4 AN5 / P4 110 5 DA0 / AN6 / ...
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Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2357 Group in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. TFP-120 FP-128B Mode ...
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Pin No. TFP-120 FP-128B Mode ...
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Pin No. 1 TFP-120 FP-128B Mode /PO5/ 5 TIOCB4/ TMCI /PO4/ 4 TIOCA4/ TMRI /PO3/ 3 TIOCD3/ TMCI /PO2/ 2 TIOCC3/ TMRI 0 70 ...
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Pin No. TFP-120 FP-128B Mode 4* 97 107 P4 98 108 P4 99 109 P4 100 110 P4 101 111 P4 DA0 102 112 P4 DA1 103 113 AV 104 114 V 105 115 P1 TIOCB2/ TCLKD 106 116 P1 ...
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Pin Functions Table 1-3 outlines the pin functions of the H8S/2357 Group. Table 1-3 Pin Functions Type Symbol Power Internal voltage V CL step-down drop pin Clock XTAL EXTAL ø Pin No. TFP-120 FP-128B I/O ...
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Type Symbol Operating mode MD control MD RES System control STBY BREQ BREQO BACK FWE* Interrupts NMI IRQ7 to IRQ0 Rev.6.00 Oct.28.2004 page 16 of 1016 REJ09B0138-0600H Pin No. TFP-120 FP-128B I/O to 115 to 125 to Input 2 113 ...
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Type Symbol TFP-120 Address bus 25 16 Data bus 48 39 CS7 to ...
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Type Symbol 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 Programmable PO15 to pulse generator PO0 (PPG) 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, ...
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Type Symbol TFP-120 A/D converter AN7 to 102 to AN0 95 ADTRG 92 D/A converter DA1, DA0 102, 101 A/D converter and D/A converter AV 103 ref I/O ports P1 to 112 to 7 ...
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Type Symbol I/O ports Notes: 1. Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390 only. 2. Applies to the H8S/2357F-ZTAT only. 3. ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. Register configuration The MAC register ...
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Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. Additional control register One 8-bit control register has been added. Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16- Mbyte (architecturally 4-Gbyte) address space in advanced mode. Rev.6.00 Oct.28.2004 page 26 of 1016 REJ09B0138-0600H H'00000000 H'00FFFFFF ...
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Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ...
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The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-5 illustrates the usage of the general ...
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Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: ...
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Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Data transfer MOV POP* LDM, STM MOVFPE, MOVTPE* Arithmetic ADD, SUB, CMP, ...
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Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL transfer POP, PUSH — LDM, STM ...
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Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation ERn (EAd) (EAs) EXR CCR ...
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Table 2-3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU MULXS Rev.6.00 Oct.28.2004 page 36 of 1016 REJ09B0138-0600H 1 Size* ...
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Type Instruction Size* Arithmetic DIVXU B/W operations DIVXS B/W CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B Logic AND B/W/L operations OR B/W/L XOR B/W/L NOT B/W/L Shift SHAL B/W/L operations SHAR SHLL B/W/L SHLR ROTL B/W/L ROTR ...
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Type Instruction Bit- BSET manipulation instructions BCLR BNOT BTST BAND BIAND BOR BIOR BXOR BIXOR BLD BILD Rev.6.00 Oct.28.2004 page 38 of 1016 REJ09B0138-0600H 1 Size* Function B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register ...
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Type Instruction Size* Bit- BST B manipulation instructions BIST B Branch Bcc — instructions JMP — BSR — JSR — RTS — System control TRAPA — instructions RTE — SLEEP — LDC B/W STC B/W 1 Function C (<bit-No.> of ...
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Type Instruction System control ANDC instructions ORC XORC NOP Block data EEPMOV.B transfer instruction EEPMOV.W Notes: 1. Size refers to the operand size. B: Byte W: Word L: Longword 2. Only register ER0, ER1, ER4, or ER5 should be used ...
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Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2-9 shows examples of instruction ...
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Table 2-4 Addressing Modes No. Addressing Mode 1 Register direct 2 Register indirect 3 Register indirect with displacement 4 Register indirect with post-increment Register indirect with pre-decrement 5 Absolute address 6 Immediate 7 Program-counter relative 8 Memory indirect (1) Register ...
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Table 2-5 Absolute Address Access Ranges Absolute Address Data address Program instruction address (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions ...
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Effective Address Calculation Table 2-6 indicates how effective addresses are calculated in each addressing mode. Table 2-6 Effective Address Calculation Rev.6.00 Oct.28.2004 page 44 of 1016 REJ09B0138-0600H ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state ...
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Bus-released state Exception-handling state RES = high Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when ...
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Table 2-7 Exception Handling Types and Priority Priority Type of Exception High Reset Trace Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE ...
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Figure 2-13 shows the stack after exception handling ends. Advanced mode SP (c) Interrupt control mode 0 Note: *Ignored when returning. Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program ...
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Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as ...
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Address bus AS RD HWR, LWR Data bus Figure 2-15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or ...
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Address bus AS RD HWR, LWR Data bus Figure 2-17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a ...
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Overview 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) The H8S/2357 F-ZTAT has eight operating modes (modes 10, 11, 14 and 15). These modes are determined by the mode pin ( and flash write ...
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The H8S/2357 F-ZTAT can only be used in modes 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change ...
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Register Configuration The H8S/2357 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD system control register (SYSCR) and a system control register 2 (SYSCR2)* Group. Table 3-3 summarizes these registers. Table 3-3 ...
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Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit cannot be modified and is always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode ...
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Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses ...
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Operating Mode Descriptions 3.3.1 Mode 1 Mode 1 is not supported in this LSI, and must not be set. 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU ...
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Mode 7 (Single-Chip Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.3.8 Modes 8 ...
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Pin Functions in Each Operating Mode The pin functions of ports vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Pin Functions in Each Mode Mode 4 Port ...
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Modes 4 and 5* (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 *3 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External ...
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Mode 10* (advanced expanded mode with on-chip ROM enabled) H'000000 H'010000 H'020000 H'FFDC00 H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF Notes: 1. External addresses when EAE = 1 in BCRL; on-chip ROM when EAE = 0. 2. Reserved area when EAE = ...
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Mode 14* User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'020000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address ...
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Notes: 1. This is a reserved space. Access to this space is inhibited. The space can be made available for use as an external address space by clearing the RAME bit of the SYSCR External addresses can ...
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ROM disabled) H'000000 H'FFDC00 H'FFFC00 H'FFFE40 H'FFFF08 H'FFFF28 H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode (H8S/2392) Modes ...
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Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode (H8S/2394) Rev.6.00 Oct.28.2004 page 68 of 1016 REJ09B0138-0600H Modes 4 and 5 (advanced expanded modes with ...
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Mode 2 (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'010000 On-chip ROM/ external address space H'040000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. External addresses when ...
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Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, ...
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Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits ...
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Table 4-2 Exception Vector Table Exception Source Power-on reset 3 Manual reset* Reserved for system use Trace Reserved for system use External interrupt Trap instruction (4 sources) Reserved for system use External interrupt 2 Internal interrupt* Notes: 1. Lower 16 ...
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Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2357 Group enters the reset state. A reset initializes the internal state of the CPU and the registers ...
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Reset Sequence The H8S/2357 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2357 Group is reset, hold the RES pin low for at least power-up. To reset the H8S/2357 ...
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Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type. The ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2357 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
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Rev.6.00 Oct.28.2004 page 80 of 1016 REJ09B0138-0600H ...
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Overview 5.1.1 Features The H8S/2357 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 ...
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Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. SYSCR NMI input IRQ input Internal interrupt request SWDTEND to TEI Legend: ISCR: IRQ sense control register IRQ enable register IER: ISR: IRQ status register ...
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Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register ...
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Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 Bit 4 Interrupt INTM1 INTM0 Control Mode — ...
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Table 5-3 Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Note: * Reserved bits. These bits cannot be modified and are always read shown in table ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 14 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 0 R/W : R/W R/W ISCRL Bit : 7 6 IRQ3SCB IRQ3SCA IRQ2SCB ...
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Bit n IRQnF Description 0 [Clearing conditions] Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn ...
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IRQn input Note: n Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 ...
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Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) Reserved TGI0A (TGR0A input ...
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Interrupt Source TGI3A (TGR3A input capture/ compare match) TGI3B (TGR3B input capture/ compare match) TGI3C (TGR3C input capture/ compare match) TGI3D (TGR3D input capture/ compare match) TCI3V (overflow 3) Reserved TGI4A (TGR4A input capture/ compare match) TGI4B (TGR4B input capture/ ...
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Interrupt Source ERI0 (receive error 0) RXI0 (reception data full 0) TXI0 (transmit data empty 0) TEI0 (transmission end 0) ERI1 (receive error 1) RXI1 (reception data full 1) TXI1 (transmit data empty 1) TEI1 (transmission end 1) ERI2 (receive ...
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Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. ...
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Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the ...
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Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Oct.28.2004 page 94 of 1016 REJ09B0138-0600H Program execution status Interrupt generated? Yes Yes NMI No I=0 Yes No IRQ0 Yes IRQ1 Yes Save PC and ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5-6 shows a ...
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Level 7 interrupt? Mask level 6 or below? Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Oct.28.2004 page 96 of 1016 REJ09B0138-0600H Program execution status Interrupt generated? Yes Yes NMI No No Yes ...
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Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Interrupt Response Times The H8S/2357 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt ...
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Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is ...
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Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ...
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Block Diagram Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller. IRQ interrupt Interrupt source On-chip clear signal supporting module 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. Selection ...
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If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt ...
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Overview The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, ...
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Other features Refresh counter (refresh timer) can be used as an interval timer External bus release function Rev.6.00 Oct.28.2004 page 104 of 1016 REJ09B0138-0600H ...
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Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 External bus control signals BREQ BACK BREQO WAIT External DRAM signals Area decoder ABWCR ASTCR BCRH BCRL Bus controller Wait controller WCRH WCRL DRAM ...
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Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Address strobe Read High write/write enable Low write Chip select 0 Chip select 1 Chip select 2/row address strobe 2 Chip select ...
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Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 6 ABW7 ABW6 Modes Initial value : 1 1 R/W : R/W R/W Mode 4 Initial value : 0 0 R/W : R/W R/W ABWCR ...
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Access State Control Register (ASTCR) Bit : 7 6 AST7 AST6 Initial value : 1 1 R/W : R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal ...
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Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit ...
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Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit ...
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Bus Control Register H (BCRH) Bit : 7 6 ICIS1 ICIS0 Initial value : 1 1 R/W : R/W R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface ...
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Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access ...
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Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a ...
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Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. 0 Wait input by WAIT pin ...
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Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 Description 0 16-bit DRAM space selected 1 8-bit DRAM space selected Bits 3 ...
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DRAM Control Register (DRAMCR) Bit : 7 6 RFSHE RCW Initial value : 0 0 R/W : R/W R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh ...
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Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared ...
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Refresh Time Constant Register (RTCOR) Bit : 7 6 Initial value : 1 1 R/W : R/W R/W RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 2-Mbyte units, and performs bus control for external space in area units. Figure ...
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Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are ...
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Memory Interfaces The H8S/2357 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct ...
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Chip Select Signals The H8S/2357 Group can output chip select signals (CS0 to CS7) to areas the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment ...
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Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus ( accessed at one time is one byte or one word, and a longword ...
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Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states cannot be ...
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Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can be inserted. ø Address ...
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Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half ( for the odd address. 0 Wait states cannot be inserted. ...
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Address bus CSn Read HWR LWR Write Note Figure 6-9 Bus Timing ...
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Address bus Read Write Note Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Oct.28.2004 page 132 of 1016 REJ09B0138-0600H T 1 ø CSn ...
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Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half ( for the odd address. 0 Wait states can be ...
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Address bus CSn Read HWR LWR Write Note Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) ...
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Address bus CSn Read HWR LWR Write Note Figure 6-13 Bus Timing ...
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Wait Control When accessing external space, the H8S/2357 Group can extend the bus cycle by inserting one or more wait states (T There are two ways of inserting wait states: program wait insertion and pin wait insertion using the ...
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Figure 6-14 shows an example of wait state insertion timing. Address bus Read Data bus HWR, LWR Write Data bus Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing The settings after a ...
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DRAM Interface 6.5.1 Overview When the H8S/2357 Group is in advanced mode, external space areas can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the ...
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Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins With DRAM Pin Setting HWR WE LCAS LCAS CS2 RAS2 CS3 RAS3 CS4 RAS4 CS5 RAS5 CAS ...
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Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and ...
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Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T inserted when DRAM space is accessed. This can be changed to two T appropriate number of T cycles according to ...
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Figure 6-17 shows an example of wait state insertion timing. ø WAIT Address bus C Sn, (RAS) CAS Read Data bus CAS Write Data bus indicates the timing of WAIT pin sampling. Notes Figure 6-17 ...
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Byte Access Control When DRAM with a 16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared MCR, the 2-CAS system is ...
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Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number ...
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RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is ...
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RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed ...
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Refresh Control The H8S/2357 Group is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR ...
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CS, (RAS) CAS, LCAS Note When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and ...
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CSn, (RAS) CAS, LCAS HWR, (WE) Note Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) 6.6 DMAC Single Address Mode and DRAM Interface When burst mode ...
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When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the T In modes other than DMAC single address mode, burst access ...
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Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait ...
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Address bus Data bus Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin ...
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Idle Cycle 6.8.1 Operation When the H8S/2357 Group accesses external space, it can insert a 1-state idle cycle (T following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately ...
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Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set idle cycle is inserted at the start of the write cycle. Figure 6-32 shows an example ...
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Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6- 33. In this case, with the setting ...
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Address bus Data bus Figure 6-34 Example of DRAM Access after External Read DRAM space read T p EXTAL Address RD RAS CAS, LCAS Data bus Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = ...
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Pin States in Idle Cycle Table 6-8 shows pin states in an idle cycle. Table 6-8 Pin States in Idle Cycle Pins A D CSn* CAS AS RD HWR LWR DACKm* Notes: 1. Remains low in DRAM space RAS ...
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Write Data Buffer Function The H8S/2357 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with ...
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Bus Release 6.10.1 Overview The H8S/2357 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there ...
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Pin States in External Bus Released State Table 6-9 shows pin states in the external bus released state. Table 6-9 Pin States in Bus Released State Pins A D CSn* CAS AS RD HWR LWR DACKm* Notes : 1. ...
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Transition Timing Figure 6-37 shows the timing for transition to the bus-released state ø Address bus Data bus AS RD HWR, LWR BREQ BACK BREQO * [1] Low level of BREQ pin is sampled at rise of ...
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Bus Arbitration 6.11.1 Overview The H8S/2357 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus ...
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Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred ...
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Resets and the Bus Controller In a power-on reset, the H8S/2357 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued manual reset*, the bus controller’s registers and ...
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Overview The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer channels. 7.1.1 Features The features of the DMAC are listed below. Choice of short address mode or full address ...
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Block Diagram A block diagram of the DMAC is shown in figure 7-1. Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A ...
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Overview of Functions Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7-1 (1) Overview of DMAC Functions (Short Address Mode) Transfer Mode Dual address mode Sequential mode 1-byte or ...
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Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Transfer Mode Normal mode Auto-request Transfer request retained internally Transfers continue for the specified number of times (1 to 65,536) Choice of burst or cycle steal transfer External request 1-byte ...
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Pin Configuration Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single ...
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Register Configuration Table 7-3 summarizes the DMAC registers. Table 7-3 DMAC Registers Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B ...