DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 152

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.2
The external space bus specifications consist of three elements: bus width, number of access states, and number of
program wait states.
The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by
the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected
functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space.
If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus
mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is
selected functions as a 2-state access space, and an area for which 3-state access is selected functions as a 3-state access
space.
With the DRAM interface and burst ROM interface, the number of access states may be determined without regard to
ASTCR.
When 2-state access space is designated, wait insertion is disabled.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait
states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected.
Table 6-3 shows the bus specifications for each basic bus interface area.
Table 6-3
Rev.6.00 Oct.28.2004 page 122 of 1016
REJ09B0138-0600H
Bus Specifications
ABWCR
ABWn
0
1
Bus Specifications for Each Area (Basic Bus Interface)
ASTCR
ASTn
0
1
0
1
Wn1
—
0
1
—
0
1
WCRH, WCRL
Wn0
—
0
1
0
1
—
0
1
0
1
Bus Width
16
8
Bus Specifications (Basic Bus Interface)
2
3
2
3
Access States
Program Wait
States
0
0
1
2
3
0
0
1
2
3