DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 892

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
TIOR5—Timer I/O Control Register 5
Rev.6.00 Oct.28.2004 page 862 of 1016
REJ09B0138-0600H
Bit
Initial value
Read/Write
:
:
:
TGR5B I/O Control
0
1
IOB3
R/W
7
0
0
1
0
1
0
1
0
1
IOB2
R/W
6
0
0
1
0
1
0
1
0
1
0
1
TGR5B
is output
compare
register
TGR5B
is input
capture
register
IOB1
R/W
5
0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is TIOCB5
pin
IOB0
R/W
TGR5A I/O Control
4
0
0
1
0
1
H'FEA2
IOA3
R/W
3
0
0
1
0
1
0
1
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
0
1
0
1
0
1
0
1
0
1
IOA2
TGR5A
is output
compare
register
TGR5A
is input
capture
register
R/W
2
0
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is TIOCA5
pin
IOA1
R/W
1
0
: Don’t care
IOA0
R/W
0
0
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
0 output at compare match
TPU5
: Don’t care

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