DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 665

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Automatic SCI Bit Rate Adjustment: When boot mode is initiated, H8S/2398 F-ZTAT chip measures the low period of
the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format
should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host
from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host
should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the
chip. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations.
Depending on the host’s transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between
the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate should be set to 9,600 or
19,200 bps.
Table 19-36 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of the
MCU’s bit rate is possible. The boot program should be executed within this system clock range.
Table 19-36 System Clock Frequencies for which Automatic Adjustment of H8S/2398
Host Bit Rate
19,200 bps
9,600 bps
F-ZTAT Bit Rate is Possible
Start
bit
Figure 19-45 Automatic SCI Bit Rate Adjustment
D0
Low period (9 bits) measured (H'00 data)
System Clock Frequency for which Automatic Adjustment
of H8S/2398 F-ZTAT Bit Rate Is Possible
16 to 20 MHz
10 to 20 MHz
D1
D2
D3
D4
D5
D6
Rev.6.00 Oct.28.2004 page 635 of 1016
D7
(1 or more bits)
High period
Stop
bit
REJ09B0138-0600H