DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 211

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3
Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table
7-4.
7.3.1
MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the
destination address register.
MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved; they are always
read as 0, and cannot be modified.
MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination
memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR).
MAR is not initialized by a reset or in standby mode.
7.3.2
IOAR is not used in full address transfer.
7.3.3
ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different
in normal mode and in block transfer mode.
ETCR is not initialized by a reset or in standby mode.
Bit
MAR
Initial value :
R/W
Bit
MAR
Initial value :
R/W
Register Descriptions (2) (Full Address Mode)
Memory Address Register (MAR)
I/O Address Register (IOAR)
Execute Transfer Count Register (ETCR)
:
:
:
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
31
15
—
—
0
*
30
14
—
—
0
*
29
13
—
—
0
*
28
12
—
—
0
*
27
11
—
—
0
*
26
10
—
—
0
*
25
—
—
0
9
*
24
—
— R/W R/W R/W R/W R/W R/W R/W R/W
0
8
*
23
*
7
*
22
*
6
*
21
*
5
*
20
*
4
*
19
*
3
*
Rev.6.00 Oct.28.2004 page 181 of 1016
18
*
2
*
17
*
1
*
16
*
0
*
REJ09B0138-0600H
*: Undefined