DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 274

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.2
8.2.1
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented,
decremented, or left fixed after a data transfer.
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented,
decremented, or left fixed after a data transfer.
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Rev.6.00 Oct.28.2004 page 244 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Register Descriptions
DTC Mode Register A (MRA)
Bit 7
SM1
0
1
Bit 5
DM1
0
1
Bit 3
MD1
0
1
:
:
Unde-
SM1
fined
—
7
Bit 6
SM0
—
0
1
Bit 4
DM0
—
0
1
Bit 2
MD0
0
1
0
1
Unde-
SM0
fined
—
6
Description
SAR is fixed
SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Description
Normal mode
Repeat mode
Block transfer mode
—
Unde-
DM1
fined
—
5
Unde-
DM0
fined
—
4
Unde-
MD1
fined
—
3
Unde-
MD0
fined
—
2
Unde-
fined
DTS
—
1
Unde-
fined
Sz
—
0