DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 256

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5.11
Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size
single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Figure 7-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read)
is performed from external 8-bit, 2-state access space to an external device.
A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the
bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after
the DMA write cycle.
Rev.6.00 Oct.28.2004 page 226 of 1016
REJ09B0138-0600H
DMAC Bus Cycles (Single Address Mode)
Address bus
Address bus
DACK
TEND
RD
ø
Figure 7-28 Example of Single Address Mode (Word Read) Transfer
DACK
TEND
Figure 7-27 Example of Single Address Mode (Byte Read) Transfer
release
RD
Bus
ø
release
Bus
DMA read
DMA read
release
Bus
release
Bus
DMA read
DMA read
release
Bus
DMA read
release
Bus
release
Bus
DMA read
Last transfer
DMA read
Last transfer
cycle
cycle
DMA
dead
release
DMA
dead
Bus
release
Bus