DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 268

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) DMAC registers are read as shown in figure 7-41, when the DMAC transfer cycle occurs immediately after the DMAC
Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered.
However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore
be made when DMAC operation is stopped.
When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register
settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop.
Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-
detected.
In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a
high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or
another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus
master clock), edge detection may not be possible and the interrupt may be ignored.
Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the medium-speed clock.
Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data
buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip
memory or internal I/O registers) are executed in parallel.
(a) Write Data Buffer Function and DMAC Register Setting
If the setting of is changed during execution of an external access by means of the write data buffer function, the external
access may not be performed normally. The register that controls external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external
access.
Rev.6.00 Oct.28.2004 page 238 of 1016
REJ09B0138-0600H
register has been read.
Transfer end/suspend interrupt (DTE = 0 and DTIE = 1)
TEND pin enable (TEE = 1)
DACK pin enable (FAE = 0 and SAE = 1)
Figure 7-41 Competition between Updating of DMAC Register and CPU Read Operations
DMA internal
address
DMA register
operation
DMA control
Note: The lower word of MAR is the updated value after the operation in [1].
ø
MAR upper
word read
Idle
CPU longword read
MAR lower
word read
[1]
Transfer
source
Read
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle