DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 409

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.4.4
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare
match register.
Table 10-5 shows the register combinations used in buffer operation.
Table 10-5 Register Combinations in Buffer Operation
When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer
general register.
This operation is illustrated in figure 10-16.
When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general
register is transferred to the buffer register.
This operation is illustrated in figure 10-17.
Buffer Operation
Channel
0
3
Buffer register
Input capture
signal
Buffer register
Figure 10-16 Compare Match Buffer Operation
Timer General Register
TGR0A
TGR0B
TGR3A
TGR3B
Figure 10-17 Input Capture Buffer Operation
Compare match signal
Timer general
register
Timer general
register
Comparator
Buffer Register
TGR0C
TGR0D
TGR3C
TGR3D
Rev.6.00 Oct.28.2004 page 379 of 1016
TCNT
TCNT
REJ09B0138-0600H