DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 386

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.6.00 Oct.28.2004 page 356 of 1016
REJ09B0138-0600H
Channel
4
Channel
5
Bit 7
IOB3
0
1
Bit 7
IOB3
0
1
Bit 6
IOB2
0
1
0
1
Bit 6
IOB2
0
1
Bit 5
IOB1
0
1
0
1
0
1
Bit 5
IOB1
0
1
0
1
0
1
Bit 4
IOB0 Description
0
1
0
1
0
1
0
1
0
1
Bit 4
IOB0 Description
0
1
0
1
0
1
0
1
0
1
TGR4B is Output disabled
output
compare
register
TGR4B is
input
capture
register
TGR5B is Output disabled
output
compare
register
TGR5B is
input
capture
register
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB4 pin
Capture input
source is TGR3C
compare match/
input capture
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB5 pin
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at generation of
TGR3C compare match/
input capture
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
(Initial value)
(Initial value)
: Don’t care
: Don’t care