DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 955

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SSR1—Serial Status Register 1
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
Transmit Data Register Empty
0
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
:
:
:
R/(W)*
TDRE
7
1
Receive Data Register Full
0
1
R/(W)*
RDRF
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
6
0
Overrun Error
0
1
R/(W)*
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
5
0
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Error Signal Status
0
1
R/(W)*
[Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS =1
[Setting condition]
When the error signal is sampled at the low level
ERS
4
0
Parity Error
0
1
R/(W)*
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
H'FF84
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Transmit End
0
1
TEND
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt
[Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu
• When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu
R
2
1
and write data to TDR
after a 1-byte serial character is sent when GM = 0
after a 1-byte serial character is sent when GM = 1
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
R
1
0
Multiprocessor Bit Transfer
0
1
MPBT
Smart Card Interface 1
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
Rev.6.00 Oct.28.2004 page 925 of 1016
REJ09B0138-0600H