DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 659

IC H8S/2300 MCU FLASH 128QFP

DF2398F20V

Manufacturer Part Number
DF2398F20V
Description
IC H8S/2300 MCU FLASH 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of DF2398F20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
87
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
DF2398F20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.16.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset,
and in hardware standby mode and software standby mode.
When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory
(programming or erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.16.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset,
in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set,
the corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1 and EBR2 together
(setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0). When on-chip flash memory is disabled,
a read will return H'00 and writes are invalid.
The flash memory block configuration is shown in table 19-33.
Bit
Initial value :
R/W
Bit
EBR1
Initial value :
R/W
Bit 7
FLER
0
1
:
:
:
:
FLER
R/W
EB7
7
0
R
7
0
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 19.19.3, Error Protection
EB6
R/W
6
0
6
0
EB5
R/W
5
0
5
0
EB4
R/W
4
0
4
0
EB3
R/W
3
0
3
0
EB2
R/W
2
0
2
0
EB1
R/W
Rev.6.00 Oct.28.2004 page 629 of 1016
1
0
1
0
EB0
R/W
0
0
0
0
(Initial value)
REJ09B0138-0600H

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