DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 505

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

For details of clock source selection, see table 14-9 in section 14.3, Operation.
Notes: 1. Initial value
14.2.7
Note: * Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER,
and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are
read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and by putting the device in standby mode or module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next
serial data can be written to TDR.
Bit
Initial value :
R/W
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
Serial Status Register (SSR)
Bit 7
TDRE
0
1
Bit 1
CKE1
0
1
:
:
R/(W)*
TDRE
7
1
Bit 0
CKE0
0
1
0
1
Description
[Clearing conditions]
[Setting conditions]
When 0 is written to TDRE after reading TDRE = 1
When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
When the TE bit in SCR is 0
When data is transferred from TDR to TSR and data can be written to TDR
R/(W)*
RDRF
6
0
Description
Asynchronous mode
Clocked synchronous
mode
Asynchronous mode
Clocked synchronous
mode
Asynchronous mode
Clocked synchronous
mode
Asynchronous mode
Clocked synchronous
mode
R/(W)*
ORER
5
0
R/(W)*
FER
4
0
R/(W)*
Internal clock/SCK pin functions as I/O port*
Internal clock/SCK pin functions as serial clock
output
Internal clock/SCK pin functions as clock output*
Internal clock/SCK pin functions as serial clock
output
External clock/SCK pin functions as clock input*
External clock/SCK pin functions as serial clock
input
External clock/SCK pin functions as clock input*
External clock/SCK pin functions as serial clock
input
PER
3
0
TEND
2
1
R
MPB
Rev.6.00 Oct.28.2004 page 475 of 1016
1
0
R
MPBT
R/W
0
0
(Initial value)
REJ09B0138-0600H
1
3
3
2