DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 358

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.13.2
Table 9-23 shows the port F register configuration.
Table 9-23 Port F Registers
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
Mode 7
Modes 4 to 6
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR
cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to H'00 in mode 7.
It retains its prior state after a manual reset*, and in software standby mode. The OPE bit in SBYCR is used to select
whether the bus control output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Note: * Modes 6 and 7 are provided in the on-chip ROM version only.
Rev.6.00 Oct.28.2004 page 328 of 1016
REJ09B0138-0600H
Bit
Initial value :
R/W
Initial value :
R/W
Mode 7*
Setting a PFDDR bit to 1 makes the corresponding port F pin PF
output pin. Clearing the bit to 0 makes the pin an input port.
Modes 4 to 6*
Pin PF
cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF
bus control outputs (AS, RD, HWR, and LWR).
Pins PF
of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port,
while clearing the bit to 0 makes the pin an input port.
2. Initial value depends on the mode.
Register Configuration
7
2
functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is
Name
Port F data direction register
Port F data register
Port F register
to PF
:
:
:
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
0
are designated as bus control input/output pins (LCAS, WAIT, BREQO, BACK, and BREQ) by means
W
W
7
0
1
W
W
6
0
0
W
W
5
0
0
Abbreviation
PFDDR
PFDR
PORTF
W
W
4
0
0
W
W
3
0
0
R/W
W
R/W
R
6
to PF
W
W
2
0
0
6
to PF
0
an output port, or in the case of pin PF
Initial Value
H'80/H'00*
H'00
Undefined
3
, which are automatically designated as
W
W
1
0
0
2
W
W
0
0
0
Address *
H'FEBE
H'FF6E
H'FF5E
1
7
, the ø