DF2398F20V Renesas Electronics America, DF2398F20V Datasheet - Page 501

• Manufacturer Part Number: DF2398F20V
• Description: IC H8S/2300 MCU FLASH 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2398F20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 87
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in
transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity
bit addition and checking is not performed, regardless of the PE bit setting.
Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous
mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in
asynchronous mode.
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is
only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not
added.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as
a stop bit; if it is 0, it is treated as the start bit of the next transmit character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit
and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked
synchronous mode.
transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit.
2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the
transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit
is even.
transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit
is odd.
Bit 5
PE
0
1
Bit 4
O/E
0
1
Bit 3
STOP
0
1
Description
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
Description
Even parity*
Odd parity*
Description
1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit
character before it is sent.
2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit
character before it is sent.
2
1
Rev.6.00 Oct.28.2004 page 471 of 1016
(Initial value)
(Initial value)
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REJ09B0138-0600H