PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 146

MCU PIC 16BIT FLASH 256K 64VQFN

PIC24FJ256DA206-I/MR

Manufacturer Part Number
PIC24FJ256DA206-I/MR
Description
MCU PIC 16BIT FLASH 256K 64VQFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets

Specifications of PIC24FJ256DA206-I/MR

Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
64-VFQFN, Exposed Pad
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
UART, SPI, USB, I2C, RS-485, RS-232
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
23
Number Of Timers
5
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
PIC24FJ256DA210 FAMILY
REGISTER 8-2:
REGISTER 8-3:
DS39969B-page 146
bit 5
bit 4
bit 3-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5-0
Note 1:
U-0
U-0
2:
This bit is automatically cleared when the ROI bit is set and an interrupt occurs.
This setting is not allowed while the USB module is enabled.
Increments or decrements of TUN<5:0> may not change the FRC frequency in equal steps over the FRC
tuning range and may not be monotonic.
PLLEN: 96 MHz PLL Enable bit
The 96 MHz PLL must be enabled when the USB or graphics controller module is enabled. This control
bit can be overridden by the PLL96MHZ (Configuration Word 2 <11>) Configuration bit.
1 = Enable the 96 MHz PLL for USB, graphics controller or HSPLL/ECPLL/FRCPLL operation
0 = Disable the 96 MHz PLL
G1CLKSEL: Display Controller Module Clock Select bit
1 = Use the 96 MHz clock as a graphics controller module clock
0 = Use the 48 MHz clock as a graphics controller module clock
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation
011110 =
·
·
·
000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =
·
·
·
100001 =
100000 = Minimum frequency deviation
U-0
U-0
CLKDIV: CLOCK DIVIDER REGISTER (CONTINUED)
OSCTUN: FRC OSCILLATOR TUNE REGISTER
W = Writable bit
‘1’ = Bit is set
TUN5
R/W-0
U-0
(1)
TUN4
R/W-0
U-0
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
R/W-0
U-0
(1)
TUN2
R/W-0
U-0
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
TUN1
R/W-0
U-0
(1)
TUN0
R/W-0
U-0
(1)
bit 8
bit 0

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