PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 323

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 22-32: G1DBEN: DATA I/O PAD ENABLE REGISTER
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
GDBEN15
GDBEN7
R/W-0
R/W-0
GDBEN<15:0>: Display Data Pads Output Enable bits
1 = Corresponding display data (GD<x>) pin is enabled
0 = Corresponding display data (GD<x>) pin is disabled
GDBEN<15:0> can be used to disable or enable specific data signals while the DPPINOE bit
(G1CON3<9>) is set.
GDBEN14
DPPINOE
GDBEN6
R/W-0
R/W-0
1
1
0
W = Writable bit
‘1’ = Bit is set
(where x = 0 to 15)
GDBEN13
GDBEN5
GDBENx
R/W-0
R/W-0
1
0
x
PIC24FJ256DA210 FAMILY
Display data signal (GD) associated with GDBENx is enabled.
Display data signal (GD) associated with GDBENx is disabled.
Display data signal (GD) associated with GDBENx is disabled.
GDBEN12
GDBEN4
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
GDBEN11
GDBEN3
R/W-0
R/W-0
GDBEN10
GDBEN2
R/W-0
R/W-0
x = Bit is unknown
GDBEN9
GDBEN1
R/W-0
R/W-0
DS39969B-page 323
GDBEN8
GDBEN0
R/W-0
R/W-0
bit 8
bit 0