PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 306

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
22.1
REGISTER 22-1:
REGISTER 22-2:
DS39969B-page 306
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-0
GCMD15
GCMD31
GCMD23
GCMD7
R/W-0
R/W-0
R/W-0
R/W-0
GFX Module Registers
GCMD<15:0>: Low GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). Writes to this register
will not trigger the loading of GCMD <31:0> to the command FIFO. For command FIFO loading, see
the G1CMDH register description.
GCMD<31:16>: High GPU Command bits
The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD<31:0>). A word write to the
G1CMDH register triggers the loading of GCMD<31:0> to the command FIFO. Byte writes to the
G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low
byte write to this register will only update the G1CMDH<7:0> bits.
GCMD14
GCMD30
GCMD22
GCMD6
R/W-0
R/W-0
R/W-0
R/W-0
G1CMDL: GPU COMMAND LOW REGISTER
G1CMDH: GPU COMMAND HIGH REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
GCMD13
GCMD29
GCMD21
GCMD5
R/W-0
R/W-0
R/W-0
R/W-0
GCMD12
GCMD28
GCMD20
GCMD4
R/W-0
R/W-0
R/W-0
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
GCMD27
GCMD19
GCMD11
GCMD3
R/W-0
R/W-0
R/W-0
R/W-0
GCMD10
GCMD26
GCMD18
GCMD2
R/W-0
R/W-0
R/W-0
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
GCMD25
GCMD17
GCMD9
GCMD1
R/W-0
R/W-0
R/W-0
R/W-0
GCMD24
GCMD16
GCMD8
GCMD0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0