PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 193

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 12-2:
FIGURE 12-3:
 2010 Microchip Technology Inc.
Note 1:
Note 1:
Set T2IF (T4IF)
Set T3IF (T5IF)
ADC Event Trigger
2:
(T5CK)
(T4CK)
T3CK
T2CK
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 10.4 “Peripheral
Pin Select (PPS)” for more information.
The ADC event trigger is available only on Timer3.
TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM
TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM
TGATE
(2)
TGATE
1
0
1
0
Reset
Reset
Equal
Equal
TMR2 (TMR4)
TMR3 (TMR5)
Comparator
Comparator
PR2 (PR4)
PR3 (PR5)
PIC24FJ256DA210 FAMILY
Q
Q
Sync
Q
Q
Gate
Sync
CK
CK
D
D
T
T
CY
CY
1x
01
00
Sync
1x
00
01
TON
TON
TCS
TGATE
TCS
TGATE
(1)
(1)
(1)
(1)
TCKPS<1:0>
1, 8, 64, 256
TCKPS<1:0>
1, 8, 64, 256
Prescaler
Prescaler
2
DS39969B-page 193
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