PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 298

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

polynomials of up of up the 32
PIC24FJ256DA210 FAMILY
21.1
21.1.1
The CRC module can be programmed for CRC
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the equa-
tion; functionally, this includes an XOR operation on the
corresponding bit in the CRC engine. Clearing the bit
disables the XOR.
For example, consider two CRC polynomials, one a
16-bit and the other a 32-bit equation.
EQUATION 21-1:
To program these polynomial into the CRC generator,
set the register bits as shown in Table 21-1.
Note that the appropriate positions are set to ‘1’ to indi-
cate they are used in the equation (for example, X26
and X23). The ‘0’ bit required by the equation is always
XORed; thus, X0 is a don’t care. For a polynomial of
length 32, it is assumed that the 32
Therefore, the X<31:1> bits do not have the 32
TABLE 21-1:
DS39969B-page 298
X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 +
CRC Control Bits
User Interface
X8 + X7 + X5 + X4 + X2 + X + 1
POLYNOMIAL INTERFACE
PLEN<4:0>
X<31:16>
X<15:0>
X16 + X12 + X5 + 1
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS
16-BIT, 32-BIT CRC
POLYNOMIALS
and
nd
order, using up to 32 bits.
nd
bit will be used.
0000 0000 0000 0001
0001 0000 0010 000X
16-Bit Polynomial
nd
bit.
01111
21.1.2
The module incorporates a FIFO that works with a vari-
able data width. Input data width can be configured to
any value between one and 32 bits using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is four words
deep. When the DWITDH bits are between 15 and 8,
the FIFO is 8 words deep. When the DWIDTH bits are
less than 8, the FIFO is 16 words deep.
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be writ-
ten into the FIFO is one byte. For example, if DWIDTH
is five, then the size of the data is DWIDTH + 1 or six.
The data is written as a whole byte; the two unused
upper bits are ignored by the module.
Once data is written into the MSb of the CRCDAT reg-
isters (that is, MSb as defined by the data width), the
value of the VWORD<4:0> bits (CRCCON1<12:8>)
increments by one. For example, if DWIDTH is 24, the
VWORD bits will increment when bit 7 of CRCDATH is
written. Therefore, CRCDATL must always be written
to before CRCDATH.
The CRC engine starts shifting data when the CRCGO
bit is set and the value of VWORD is greater than zero.
Each word is copied out of the FIFO into a buffer regis-
ter, which decrements VWORD. The data is then
shifted out of the buffer. The CRC engine continues
shifting at a rate of two bits per instruction cycle, until
VWORD reaches zero. This means that for a given
data width, it takes half that number of instructions for
each word to complete the calculation. For example, it
takes 16 cycles to calculate the CRC for a single word
of 32-bit data.
When VWORD reaches the maximum value for the
configured value of DWIDTH (4, 8 or 16), the CRCFUL
bit becomes set. When VWORD reaches zero, the
CRCMPT bit becomes set. The FIFO is emptied and
the VWORD<4:0> bits are set to ‘00000’ whenever
CRCEN is ‘0’.
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
Bit Values
DATA INTERFACE
0000 0100 1100 0001
0001 1101 1011 011x
 2010 Microchip Technology Inc.
32-Bit Polynomial
11111