PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 307

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 22-3:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-8
bit 7-5
bit 4-0
PUBPP2
R/W-0
R/W-0
G1EN
G1EN: Module Enable bit
1 = Display module is enabled
0 = Display module is disabled
Unimplemented: Read as ‘0’
G1SIDL: Stop in Idle bit
1 = Display module stops in Idle mode
0 = Display module does not stop in Idle mode
GCMDWMK<4:0>: Command FIFO Watermark bits
Sets the command watermark level that triggers the CMDLVIF interrupt and sets the CMDLV flag;
GCMDWMK<4:0> (10000 = Reserved)
10000 = If the number of commands present in the FIFO goes from 16 to 15 commands, the CMDLVIF
01111 =
.
.
.
00001 = If the number of commands present in the FIFO goes from 1 to 0 commands, the CMDLVIF
00000 = CMDLVIF interrupt will not trigger and the CMDLV flag will not be set
PUBPP<2:0>: GPU bits-per-pixel (bpp) Setting bits
Other = Reserved
100 = 16 bits-per-pixel
011 = 8 bits-per-pixel
010 = 4 bits-per-pixel
001 = 2 bits-per -pixel
000 = 1-bit -per-pixel
GCMDCNT<4:0>: Command FIFO Occupancy Status bits
When the FIFO is full, any additional commands written to the FIFO are discarded.
10000 = 16 commands are present in the FIFO
01111 = 15 commands are present in the FIFO
.
.
.
0001 = 1 command is present in the FIFO
0000 = 0 command is present in the FIFO
PUBPP1
R/W-0
U-0
—
G1CON1: DISPLAY CONTROL REGISTER 1
interrupt will trigger and the CMDLV flag will be set
interrupt will trigger and CMDLV flag will be set
interrupt will trigger and the CMDLV flag will be set
f the number of commands present in the FIFO goes from 15 to 14 commands, CMDLVIF
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
PUBPP0
G1SIDL
R/W-0
R/W-0
GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0
GCMDCNT4
R-0, HSC
R/W-0
PIC24FJ256DA210 FAMILY
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
GCMDCNT3
R-0, HSC
R/W-0
GCMDCNT2
R-0, HSC
R/W-0
x = Bit is unknown
GCMDCNT1
R-0, HSC
R/W-0
DS39969B-page 307
GCMDCNT0
R-0, HSC
R/W-0
bit 8
bit 0