PIC24FJ256DA206-I/MR Microchip Technology, PIC24FJ256DA206-I/MR Datasheet - Page 314

• Manufacturer Part Number: PIC24FJ256DA206-I/MR
• Description: MCU PIC 16BIT FLASH 256K 64VQFN
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256DA206-I/MR

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 64-VFQFN, Exposed Pad
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 96 KB
• Interface Type: UART, SPI, USB, I2C, RS-485, RS-232
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240001, DM240312, DV164039
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256DA210 FAMILY
REGISTER 22-12: G1W2ADRH: GPU WORK AREA 2 START ADDRESS REGISTER HIGH
REGISTER 22-13: G1PUW: GPU WORK AREA WIDTH REGISTER
REGISTER 22-14: G1PUH: GPU WORK AREA HEIGHT REGISTER
DS39969B-page 314
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-11
bit 10-0
W2ADR23
R/W-0
PUW7
R/W-0
PUH7
R/W-0
U-0
U-0
U-0
—
—
—
Unimplemented: Read as ‘0’
PUH<10:0>: GPU Work Area Height bits (in pixels)
Unimplemented: Read as ‘0’
PUW<10:0>: GPU Work Area Width bits (in pixels)
Unimplemented: Read as ‘0’
W2ADR<23:16>: GPU Work Area 2 Start Address High bits
Work area address must point to an even byte address in memory.
W2ADR22
R/W-0
R/W-0
PUW6
PUH6
R/W-0
U-0
U-0
—
U-0
—
—
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
W2ADR21
R/W-0
PUH5
R/W-0
PUW5
U-0
R/W-0
U-0
—
—
U-0
—
R/W-0
PUH4
W2ADR20
PUW4
R/W-0
U-0
U-0
—
R/W-0
—
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
PUH3
R/W-0
PUW3
W2ADR19
U-0
U-0
—
—
R/W-0
U-0
—
PUH10
PUW10
R/W-0
R/W-0
PUH2
W2ADR18
R/W-0
R/W-0
PUW2
R/W-0
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
W2ADR17
R/W-0
R/W-0
PUH9
PUH1
R/W-0
PUW9
R/W-0
PUW1
R/W-0
U-0
—
W2ADR16
R/W-0
R/W-0
PUH8
PUH0
PUW8
PUW0
R/W-0
R/W-0
R/W-0
U-0
—
bit 8
bit 0
bit 8
bit 0
bit 8
bit 0