HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 13

IC H8S MCU FLASH 128K 128QFP

HD64F2636UF20

Manufacturer Part Number
HD64F2636UF20
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2636UF20

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Item
16.2.6 Transmit Wait
Cancel Register
(TXCR)
16.2.7 Transmit
Acknowledge Register
(TXACK)
16.2.8 Abort
Acknowledge Register
(ABACK)
16.2.16 Unread
Message Status
Register (UMSR)
16.2.17 Local
Acceptance Filter
Masks (LAFML,
LAFMH)
LAFMH Bits 7 to 0 and
15 to 13
LAFMH Bits 9 and 8,
LAFML Bits 15 to 0
16.2.20 Module Stop
Control Register C
(MSTPCRC)
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Page
626
627
628
641
643
650
Revision (See Manual for Details)
Table amended
Bit y: TXCRx
0
1
Table amended
Bit y: TXACKx
0
1
Table amended
Bit y: ABACKx
0
1
Table amended
Bit x: UMSRx
0
1
Table amended
Bit x: LAFMHx
0
1
Table amended
Bit y: LAFMHx
0
1
Note amended
Note: * The MSTPC2 is not available and is reserved in the
LAFMLy
H8S/2635 Group.
Description
Transmit message cancellation idle state in corresponding mailbox
[Clearing condition]
TXPR cleared for corresponding mailbox (transmit message cancellation)
Description
[Clearing condition]
Completion of message transmission for corresponding mailbox
Description
[Clearing condition]
Completion of transmit message cancellation for corresponding mailbox
Description
[Clearing condition]
Unread receive message is overwritten by a new message
[Setting condition]
Description
Stored in MC0 and MD0 (receive-only mailbox) depending on bit match
between MC0 message identifier and receive message identifier
Stored in MC0 and MD0 (receive-only mailbox) regardless of bit match
between MC0 message identifier and receive message identifier
Description
Stored in MC0 (receive-only mailbox) depending on bit match between MC0
message identifier and receive message identifier
Stored in MC0 (receive-only mailbox) regardless of bit match between MC0
message identifier and receive message identifier
Completion of TXPR clearing (when transmit message is canceled
normally)
Writing 1
Writing 1
Writing 1
When a new message is received before RXPR is cleared
(x = 15 to 1, y = 15 to 9 and 7 to 0)
(x = 15 to 1, y = 15 to 9 and 7 to 0)
(x = 15 to 1, y = 15 to 9 and 7 to 0)
(x = 1 and 0, y = 15 to 0)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Page xiii of l
(x = 15 to 0)
(x = 15 to 5)

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