HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 246

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is
repeated.
8.2.6
Bit
Initial value
R/W
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7
The DTC enable registers comprise seven 8-bit readable/writable registers, DTCERA to DTCERG
with bits corresponding to the interrupt sources that can control enabling and disabling of DTC
activation. These bits enable or disable DTC service for the corresponding interrupt sources.
The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode.
Page 196 of 1458
Bit
Initial value
R/W
DTC Transfer Count Register B (CRB)
DTC Enable Registers (DTCER)
:
:
:
:
:
:
15
⎯
*
DTCE7
R/W
14
⎯
7
0
*
13
⎯
*
DTCE6
R/W
6
0
12
⎯
*
11
⎯
*
DTCE5
R/W
5
0
10
⎯
*
⎯
9
*
DTCE4
R/W
4
0
⎯
8
*
DTCE3
⎯
7
*
R/W
3
0
⎯
6
*
DTCE2
⎯
5
*
R/W
2
0
H8S/2639, H8S/2638, H8S/2636,
⎯
4
*
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
DTCE1
⎯
R/W
3
*
1
0
⎯
2
*
*: Undefined
DTCE0
May 28, 2010
R/W
⎯
1
*
0
0
⎯
0
*