HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 193

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 4
MSTPC4
0
1
6.3
The operation flow from break condition setting to PC break interrupt exception handling is shown
in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and 6.3.2, PC Break Interrupt Due to
Data Access, taking the example of channel A.
6.3.1
(1) Initial settings
(2) Satisfaction of break condition
(3) Interrupt handling
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ Set the break address in BARA. For a PC break caused by an instruction fetch, set the
⎯ Set the break conditions in BCRA.
⎯ When the instruction at the set address is fetched, a PC break request is generated
⎯ After priority determination by the interrupt controller, PC break interrupt exception
address of the first instruction byte as the break address.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5 to 3 (BAMA2 to BAMA0): Set the address bits to be masked.
BCRA bits 2, 1 (CSELA1, CSELA0): Set 00 to specify an instruction fetch as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
handling is started.
Operation
PC Break Interrupt Due to Instruction Fetch
Description
PC break controller module stop mode is cleared
PC break controller module stop mode is set
Section 6 PC Break Controller (PBC)
(Initial value)
Page 143 of 1458