HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 863
HD64F2636UF20
Manufacturer Part Number
HD64F2636UF20
Description
IC H8S MCU FLASH 128K 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2636UF20
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
21B.7.3 Erase Block Register 1 (EBR1)
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be erased. Other
blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can be set. Do not
set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be automatically
cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and writes are
invalid.
The flash memory erase block configuration is shown in table 21B-7.
21B.7.4 Erase Block Register 2 (EBR2)
EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low
level is input to the FWE pin. Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set, even
though a high level is input to pin FWE. When a bit in EBR2 is set to 1, the corresponding block
can be erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2
combined can be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and
EBR2 to be automatically cleared to 0. On the H8S/2638 and H8S/2639 bits 7 to 4 are reserved,
and on the H8S/2630 bits 7 and 6 are reserved. Only 0 may be written to these reserved bits. When
on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
The flash memory erase block configuration is shown in table 21B-7.
Note: * Valid on the H8S/2630. On the H8S/2638 and H8S/2639 these bits are reserved and only 0
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Initial value:
Initial value:
may be written to them.
R/W:
R/W:
Bit:
Bit:
R/W
R/W
EB7
—
7
0
7
0
R/W
R/W
EB6
—
6
0
6
0
EB13 *
R/W
R/W
EB5
5
0
5
0
EB12 *
R/W
R/W
EB4
4
0
4
0
(H8S/2638 Group, H8S/2639 Group, H8S/2630 Group)
EB11
R/W
R/W
EB3
3
0
3
0
EB10
R/W
R/W
EB2
2
0
2
0
R/W
R/W
EB1
EB9
1
0
1
0
Section 21B ROM
Page 813 of 1458
R/W
R/W
EB0
EB8
0
0
0
0
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