HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 1443

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SCR0—Serial Control Register 0
SCR1—Serial Control Register 1
SCR2—Serial Control Register 2
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Transmit Interrupt Enable
Receive Interrupt Enable
Bit
Initial value
Read/Write
0
1
0
1
Transmit-data-empty interrupt
(TXI) request disabled *
Transmit-data-empty interrupt
(TXI) request enabled
Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request disabled *
Receive-data-full interrupt (RXI)
request and receive-error interrupt
(ERI) request enabled
R/W
TIE
7
0
1
2
R/W
RIE
6
0
Transmit Enable
0
1
R/W
TE
Receive Enable
5
0
Transmission disabled *
Transmission enabled *
0
1
Multiprocessor Interrupt Enable
0
1
Reception disabled *
Reception enabled *
Transmit End Interrupt Enable
Multiprocessor interrupts disabled (normal reception mode)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts enabled *
Receive interrupt (RXI) requests, receive-error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to
1 is received
0
1
R/W
RE
Clock Enable 1 and 0
Transmit-end interrupt (TEI) request disabled *
Transmit-end interrupt (TEI) request enabled *
4
0
0
1
0
1
0
1
Asynchronous
mode
Clocked
synchronous mode
Asynchronous
mode
Clocked
synchronous mode
Asynchronous
mode
Clocked
synchronous mode
Asynchronous
mode
Clocked
synchronous mode
MPIE
4
R/W
3
H'FF7A
H'FF82
H'FF8A
6
5
3
0
TEIE
R/W
2
0
Internal clock/SCK pin
functions as I/O port
Internal clock/SCK pin
functions as serial clock output
functions as clock output*
Internal clock/SCK pin
functions as serial clock output
External clock/SCK pin
functions as clock input*
External clock/SCK pin
functions as serial clock input
External clock/SCK pin
functions as clock input*
External clock/SCK pin
functions as serial clock input
Internal clock/SCK pin
7
Appendix B Internal I/O Register
CKE1
R/W
1
0
8
8
CKE0
Page 1393 of 1458
R/W
0
0
10
10
9
SCI0
SCI1
SCI2