HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 197

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
6.3.6
Caution is required in the following cases, as instruction execution is one state later than usual.
(1) When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a
(2) When break interruption by instruction fetch is set, the set address indicates on-chip ROM or
(3) When break interruption by instruction fetch is set and a break interrupt is generated, if the
(4) When break interruption by instruction fetch is set and a break interrupt is generated, if the
REJ09B0103-0800 Rev. 8.00
May 28, 2010
one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on-
chip ROM or RAM is always delayed by one state.
RAM space, and that address is used for data access, the instruction that executes the data
access is one state later than in normal operation.
executing instruction immediately preceding the set instruction has one of the addressing
modes shown below, and that address indicates on-chip ROM or RAM, and that address is
used for data access, the instruction will be one state later than in normal operation.
@ERn, @(d:16,ERn), @(d:32,ERn), @-ERn/ERn+, @aa:8, @aa:24, @aa:32, @(d:8,PC),
@(d:16,PC), @@aa:8
executing instruction immediately preceding the set instruction is NOP or SLEEP, or has
#xx,Rn as its addressing mode, and that instruction is located in on-chip ROM or RAM, the
instruction will be one state later than in normal operation.
When Instruction Execution Is Delayed by One State
Section 6 PC Break Controller (PBC)
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