HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 506

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
0
1
Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
0
1
Notes: 1. The TDRE flag in SSR is fixed at 1.
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
0
1
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
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flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
2. In this state, serial transmission is started when transmit data is written to TDR and the
2. Serial reception is started in this state when a start bit is detected in asynchronous
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transfer format before setting the TE bit
to 1.
retain their states.
mode or serial clock input is detected in clocked synchronous mode.
SMR setting must be performed to decide the transfer format before setting the RE bit
to 1.
Description
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled*
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
Description
Transmission disabled *
Transmission enabled *
Description
Reception disabled *
Reception enabled *
2
1
2
1
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
(Initial value)
(Initial value)
(Initial value)
May 28, 2010