HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 708

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 Controller Area Network (HCAN)
• Receive-only mailbox (mailbox 0)
Mailbox (Message Control/Data (MCx[x], MDx[x]) Initial Settings: After power is supplied,
all registers and RAM (message control/data, control registers, status registers, etc.) are initialized.
Message control/data (MCx[x], MDx[x]) only are in RAM, and so their values are undefined.
Initial values must therefore be set in all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: Either of the following message transmission
methods can be selected with the message transmission method bit (MCR2) in the master control
register (MCR):
a. Transmission order determined by message identifier priority
b. Transmission order determined by mailbox number priority
When a is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), the message with the highest priority set in the message identifier (MCx[5] to MCx[8]) is
stored in the transmit buffer. CAN bus arbitration is then carried out for the message in the
transmit buffer, and message transmission is performed when the transmission right is acquired.
When the TXPR bit is set, internal arbitration is performed again, and the highest-priority message
is found and stored in the transmit buffer.
When b is selected, if a number of messages are designated as waiting for transmission (TXPR =
1), messages are stored in the transmit buffer in low-to-high mailbox order (priority order:
mailbox 1 > mailbox 15). CAN bus arbitration is then carried out for the messages in the transmit
buffer, and message transmission is performed when the bus is acquired.
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Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for reception use. When setting mailboxes for reception, to improve message
transmission efficiency, high-priority messages should be set in low-to-high mailbox order
(priority order: mailbox 1 > mailbox 15).
No setting is necessary, as this mailbox is always used for reception.
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010