HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 553

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
13.4
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 13-13 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC to
perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC. The DTC cannot be activated by a TEI interrupt request.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can
activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data
transfer is performed by the DTC. The DTC cannot be activated by an ERI interrupt request.
Table 13-12 SCI Interrupt Sources
Channel
0
1
2
Note: * This table shows the initial state immediately after a reset. Relative priorities among
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
REJ09B0103-0800 Rev. 8.00
May 28, 2010
channels can be changed by means of the interrupt controller.
SCI Interrupts
Interrupt
Source Description
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
ERI
RXI
TXI
TEI
Interrupt due to receive error (ORER, FER, or PER)
Interrupt due to receive data full state (RDRF)
Interrupt due to transmit data empty state (TDRE)
Interrupt due to transmission end (TEND)
Interrupt due to receive error (ORER, FER, or PER)
Interrupt due to receive data full state (RDRF)
Interrupt due to transmit data empty state (TDRE)
Interrupt due to transmission end (TEND)
Interrupt due to receive error (ORER, FER, or PER)
Interrupt due to receive data full state (RDRF)
Interrupt due to transmit data empty state (TDRE)
Interrupt due to transmission end (TEND)
Section 13 Serial Communication Interface (SCI)
DTC
Activation
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
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Priority *
High
Low