HD64F2636UF20 Renesas Electronics America, HD64F2636UF20 Datasheet - Page 624

• Manufacturer Part Number: HD64F2636UF20
• Description: IC H8S MCU FLASH 128K 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2636UF20

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.2.8
DDCSWR is an 8-bit readable/writable register that is used to initialize the IIC module.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bits 7 to 4—Reserved: Should always be written with 0.
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be written to in accordance with the setting.
Bit 3
CLR3
0
1
Page 574 of 1458
Bit
Initial value :
R/W
Notes: 1. Should always be written with 0.
DDC Switch Register (DDCSWR)
2. Always read as 1.
2
C Bus Interface [Option]
CLR2
0
1
—
Bit 2
:
:
R/(W)*
⎯
7
0
1
Bit 1
CLR1
—
0
1
—
R/(W)*
⎯
6
0
1
Bit 0
CLR0
—
0
1
0
1
—
R/(W)*
⎯
5
0
1
R/(W)*
Description
Setting prohibited
Setting prohibited
IIC0 internal latch cleared
IIC1 internal latch cleared
IIC0 and IIC1 internal latches cleared
Invalid setting
⎯
4
0
1
CLR3
W*
3
1
2
CLR2
W*
2
1
2
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
CLR1
W*
1
1
2
May 28, 2010
CLR0
W*
0
1
2