73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 101

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
ATR Timeout Registers (ATRLsB): 0xFE20  0x00, (ATRMsB): 0xFE1F  0x00
These registers form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading
edge of the first character and leading edge of the last character of the ATR response. Timer is enabled
when the RCVATR is set and starts when leading edge of the first start bit is received and disabled when
the RCVATR is cleared. An ATR timeout is generated if this time is exceeded.
MSB
MSB
TS Timeout Register (STSTO): 0xFE21  0x00
The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of
the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is
de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).
Reset Time Register (RLength): 0xFE22  0x70
Time in ETUs that the hardware delays the de-assertion of RST. If set to 0 and RSTCRD = 0, the hardware
adds no extra delay and the hardware will release RST after VCCOK is asserted during power-up. If set to 1,
it will delay the release of RST by the time in this register. When the firmware sets the RSTCRD bit, the
hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the hardware will release RST
after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to instructing the power to be applied
to the smart card, the hardware will not release RST after power-up until RLen after the firmware clears the
RSTCRD bit. This provides a means to power up the smart card and hold it in reset until the firmware wants
to release the RST to the selected smart card. Works with the selected smart card interface.
Rev. 1.4
ATRTO.15
ATRTO.7
MSB
TST0.7
MSB
RLen.7
ATRTO.14
ATRTO.6
TST0.6
RLen.6
ATRTO.13
ATRTO.5
TST0.5
RLen.5
Table 104: The ATRMsB Register
Table 103: The ATRLsB Register
Table 105: The STSTO Register
Table 106: The RLength Register
ATRTO.12
ATRTO.4
TST0.4
RLen.4
TST0.3
ATRTO.11
ATRTO.3
RLen.3
TST0.1
ATRTO.10 ATRTO.9 ATRTO.8
RLen.1
ATRTO.1
TST0.2
RLen.2
ATRTO.2 ATRTO.0
73S1210F Data Sheet
TST0.0
RLen.0
LSB
LSB
LSB
LSB
101