73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 78

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
78
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high.
4. Set IO Bit low and IODir = Output.
5. Set TX/RX Bit to TX mode.
6. Reload Rlength Counter.
7. Set IO Bit High and IODir = Output.
8. Clear CLK Stop and CLK Stop level.
RLength Interrupt
CLK Stop Level
RLength Count
TX/RX Mode Bit
(Rlength = 9)
Note: Data in TX fifo should not be Empty here.
TX = '1'
Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode
CLK Stop
Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high in Interrupt routine.
4. Set TX/RX Bit to TX mode.
5. Reload Rlength Counter.
6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.
7. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
IODir Bit
IO Bit
RLength Count - was set for length of ATR
RLength Interrupt
CLK Stop Level
CLK
TX/RX Mode Bit
generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.
IO
TX = '1'
Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to
Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to
CLK Stop
IODir Bit
IO Bit
I2CMode = 1: Data to/from Card
I2CMode = 0: Data from TX fifo
generate the Stop bit in Synchronous Mode. SYCKST is bit 7 of STXCTL register.
CLK
IO
Data from Card -end of ATR
TX/RX mode
1
RLength Count MAX
I2CMode = 1:ACK Bit (to/from card)
2
1
I2CMode = 0: Data from TX fifo
Count MAX
RLength
3
2
3
4
4
5
5
6
6
RLen=0
6
7
Rlen=1
Data from TX FIFO
7
START Bit
8
STOP Bit
DS_1210F_001
Rev. 1.4