73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 90

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
External Smart Card Control Register (SCECtl): 0xFE0B  0x00
This register is used to directly set and sample signals of External Smart Card interface. There are three
modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per
the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for
I
should be handled via the I
used for C4, C8 functions if necessary.
90
2
C clock stop and start. Control for Reset (to make RST signal), activation control, voltage select, etc.
SCECtl.7
SCECtl.6
SCECtl.5
SCECtl.4
SCECtl.3
SCECtl.2
SCECtl.1
SCECtl.0
MSB
Bit
–
SCLKOFF
SCLKLVL
Symbol
SIOD
SIO
–
–
–
–
–
2
C interface when using external 73S8010 devices. USR(n) pins shall be
External Smart Card I/O. Bit when read indicates state of pin SIO for SIOD
= 1 (Caution, this signal is not synchronized to the MPU clock), when
written, sets the state of pin SIO for SIOD = 0. Ignored if not in bypass or
sync modes. In sync mode, this bit will contain the value of IO pin on the
latest rising edge of SCLK.
1 = input, 0 = output. External Smart Card I/O Direction control. Ignored if
not in bypass or sync modes.
Sets the state of SCLK when disabled by SCLKOFF bit. If in bypass mode,
this bit directly controls the state of SCLK.
0 = SCLK enabled, 1 = SCLK disabled. When disabled, SCLK level is
determined by SCLKLVL. This bit has no effect if in bypass mode.
SIO
Table 83: The SCECtl Register
SIOD
–
Function
–
SCLKLVL
DS_1210F_001
SCLKOFF
Rev. 1.4
LSB