73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 72

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
1.7.15.2
A card insertion event generates an interrupt to the firmware, which is then responsible for the
configuration of the electrical interface, the UART and activation of the card. The activation sequencer
goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous
activation timing diagram is shown in
Figure 16. After the card reset is de-asserted, the firmware instructs the hardware to look for a TS byte
that begins the ATR response. If a response is not provided within the pre-programmed timeout period,
an interrupt is generated and the firmware can then take appropriate action, including instructing the
73S1210F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes
through the power down sequence as defined in the ISO 7816-3 specification. If an ATR response is
received, the hardware looks for a TS byte that determines direct/inverse convention. The hardware
handles the indirect convention conversion such that the embedded firmware only receives direct
convention. This feature can be disabled by firmware within
break generation is performed on the TS byte unless disabled by firmware. If during the card session, a
card removal, over-current or other error event is detected, the hardware will automatically perform the
deactivation sequence and then generate an interrupt to the firmware. The firmware can then perform
any other error handling required for proper system operation. Smart card RST, I/O and CLK, C4, C8
shall be low before the end of the deactivation sequence. Figure 17 shows the timing for a deactivation
sequence.
72
t1: SELSC.1 bit set (selects internal ICC interface) and a non-zero value in VCCSEL bits (calling for a
value of Vcc of 1.8, 3.0, or 5.0 volts) will begin the activation sequence. t1 is the time for Vcc to rise
to acceptable level, declared as Vcc OK (bit VCCOK gets set). This time depends on filter capacitor
value and card Icc load.
tto: The time allowed for Vcc to rise to Vcc OK status after setting of the VCCSEL bits. This time is
generated by the VCCTMR counter. If Vcc OK is not set, (bit VCCOK) at this time, a deactivation will
be initiated. VCCSEL bits are not automatically cleared. The firmware must clear the VCCSEL bits
before starting a new activation.
t2: Time from
= 0. If RDYST = 1, t2 starts when VCCOK = 1.
t3: Time from IO = high to CLK start, typically 2-3 CLK cycles.
t4: Time allowed for start of CLK to de-assertion of RST. Programmable by the
t5: Time allowed for ATR timeout, set by the
Note: If the RSTCRD bit is set, RST is asserted (low). Upon clearing RSTCRD bit, RST will be
de-asserted after t4.
RSTCRD bit
VCCOK bit
Answer to Reset Processing
VCCSEL
SELSC
VCC
RST
CLK
bits
bits
IO
VccTmr
timeout and VCC OK to IO reception (high), typically 2-3 CLK cycles if RDYST
t1
tto
t2
t3
STSTO
t4
register.
SByteCtl
register. Parity checking and
t5
t4
RLength
DS_1210F_001
See Note
ATR starts
register.
Rev. 1.4