73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 49

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
1.7.9
The 73S1210F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins
are inputs until they are configured for the desired direction. The pins are configured and controlled by
the
or output with the bits of the
associated with each group of USR pins. USR pins 0 to 7 are multiple use pins that can be used for
general purpose I/O, external interrupts and timer control. Table 48 shows the configuration for a USR
pin through its associated bit in its UDIR register. Values read from and written into the GPIO ports use
the data registers
until any write to the corresponding UDIR register is performed. This insures all USR pins are set to a
known value until set by the firmware. Unused USR pins can be set for output if unused and
unconnected to prevent them from floating. Alternatively, unused USR pins can be set for input and tied
to ground or V
Four XRAM SFR registers (USRIntTCtl0, USRIntTCtl1, USRIntTCtl2, and USRIntTCtl3) control the use of
the USR [7:0] pins. Each of the USR [7:0] pins can be configured as GPIO or individually be assigned an
internal resource such as an interrupt or a timer/counter control. Each of the four registers contains two
3-bit configuration words named UxIS (where x corresponds to the USR pin). The control resources
selectable for the USR pins are listed in
to the same resource, the resources are combined using a logical OR.
Note: x denotes the corresponding USR pin. Interrupt edge or level control is assigned in the IT0 and IT1
bits in the TCON register.
Rev. 1.4
USR70
User (USR) Ports
USR_0…USR_7
and
USR Pin Group
Table 47: Direction Registers and Internal Resources for DIO Pin Groups
DD
UDIR70
.
USR70.
UxIS Value
SFRs. Each pin declared as USR can be configured independently as an input
Table 49: Selectable Controls Using the UxIS Bits
Note: After reset, all USR pins are defaulted as inputs and pulled up to VDD
UDIR70
0
1
2
3
4
5
6
7
Multi-use
USR Pin Function
Type
register. Table 47 lists the direction registers and configurability
Interrupt 0 falling edge/low level on USRx
Table 48: UDIR Control Bit
Resource Selected for USRx Pin
None
None
T0 (counter0 gate/clock)
T1 (counter1 gate/clock)
Interrupt 0 rising edge/high level on USRx
Interrupt 1 rising edge/high level on USRx
Interrupt 1 falling edge/low level on USRx
Table 50
Direction
Register
UDIR70
Name
through
output
Table
0
Direction
0x91 [7:0]
UDIR Bit
Location
Register
(SFR)
53. If more than one input is connected
input
1
Register
USR70
Name
Data
73S1210F Data Sheet
0x90 [7:0]
Location
Register
(SFR)
Data
49