73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 17

no-image

73S1210F-68IM/F

Manufacturer Part Number
73S1210F-68IM/F
Description
IC SMART CARD READER 68-QFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of 73S1210F-68IM/F

Core Processor
80515
Core Size
8-Bit
Speed
24MHz
Connectivity
I²C, SmartCard, UART/USART
Peripherals
LED, POR, WDT
Number Of I /o
8
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
73S1210F-68IM/F
Manufacturer:
TERIDIAN
Quantity:
7 728
DS_1210F_001
Register
FLSHCTL
TRIMPCtl
FUSECtl
SECReg
Rev. 1.4
Address
0xFFD1
0xFFD2
0xFFD7
0xB2
SFR
R/W
R/W
R/W
R/W
R/W
W
W
W
W
R
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
0x54 value will set up for security fuse control. All other values are
reserved and should not be used.
0xA6 value will cause the selected fuse to be blown. All other values
will stop the burning process.
Bit 7 (PARAMSEC):
0 – Normal operation.
1 – Enable permanent programming of the security fuses.
Bit 5 (SECPIN):
Indicates the state of the SEC pin. The SEC pin is held low by a
pull-down resistor. The user can force this pin high during boot
sequence time to indicate to firmware that sec mode 1 is desired.
Bit 1 (SECSET1):
See the Program Security section.
Bit 0 (SECSET0):
See the Program Security section.
Table 5: Program Security Registers
Description
73S1210F Data Sheet
17

Related parts for 73S1210F-68IM/F