73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 96

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
FD Control Register (FDReg): 0xFE13  0x11
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The
maximum supported F/D ratio is 4096.
The values given below are used by the ETU divider to create the ETU clock. The entries that are not
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are
within 1% of the target value.
96
Note: values marked with ⊕ are not included in the ISO definition and arbitrary values have been
assigned.
FI (code)
Fi (ratio)
FCLK max
FI(code)
Fi(ratio)
FCLK max
DI(code)
Di(ratio)
DI(code)
Di(ratio)
MSB
FDReg.7
FDReg.6
FDReg.5
FDReg.4
FDReg.3
FDReg.2
FDReg.1
FDReg.0
FVAL.3
Bit
0000
372
4
1000
512⊕
5⊕
0000
1⊕
1000
12
FVAL.2
Symbol
DVAL.3
DVAL.2
DVAL.1
DVAL.0
FVAL.3
FVAL.2
FVAL.1
FVAL.0
Table 92: Divider Ratios Provided by the ETU Counter
0001
372
5
1001
512
5
0001
1
1001
20
FVAL.1
Refer to the Table 93 above. This value is converted per the table to
set the divide ratio used to generate the baud rate (ETU). Default,
also used for ATR, is 0001 (Fi = 372). This value is used by the
selected interface.
Refer to Table 93 above. This value is used to set the divide ratio
used to generate the smart card CLK. Default, also used for ATR, is
0001 (Di = 1).
Table 91: The FDReg Bit Functions
Table 90: The FDReg Register
0010
558
6
1010
768
7.5
0010
2
1010
16⊕
FVAL.0
0011
744
8
1011
1024
10
0011
4
1011
16⊕
DVAL.3
0100
1116
12
1100
1536
15
0100
8
1100
16⊕
Function
DVAL.2
0101
1488
16
1101
2048
20
0101
16
1101
16⊕
DVAL.1
0110
1860
20
1110
2048⊕
20⊕
0110
32
1110
16⊕
DVAL.0
DS_1210F_001
LSB
0111
1860⊕
20⊕
1111
2048⊕
20⊕
0111
32⊕
1111
16⊕
Rev. 1.4