73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 23

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
The master clock control register enables different sections of the clock circuitry and specifies the value
of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper
operation of some of the peripheral blocks according to the following formula:
Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 10. The possible
crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 11.
Master Clock Control Register (MCLKCtl): 0x8F  0x0A
The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable
by configuring the MPU Clock Control register.
Rev. 1.4
MCLKCtl.7
MCLKCtl.6
MCLKCtl.5
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCLKCtl.1
MCLKCtl.0
Bit
MSB
HSOEN
Symbol
HSOEN
MCT.2
MCT.1
MCT.0
KBEN
SCEN
Table 11: Frequencies and Mcount Values for MCLK = 96MHz
–
–
KBEN
High-speed oscillator disable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. Do not set this bit = 1.
1 = Disable the keypad logic clock.
1 = Disable the smart card logic clock.
This value determines the ratio of the VCO frequency (MCLK) to the
high-speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)* F
that MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLK = (Mcount * 2 + 4) * F
SCEN
Table 12: The MCLKCtl Register
F
XTAL
12.00
–
9.60
8.00
6.86
6.00
(MHz)
–
XTAL
Mcount (N)
XTAL
. The default value is MCount = 2h such
MCT.2
Function
2
3
4
5
6
= 96MHz
MCT.1
MCT.0
73S1210F Data Sheet
LSB
23