73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 125

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
Revision History
Rev. 1.4
Revision
1.0
1.1
1.2
Date
5/10/2007
11/6/2007
12/15/2008
Description
First publication.
In
In
and 32-cycle references.
In
must be bound between a value of 1 to 7. The possible crystal or external
clock are shown in Table 12.“ to “Mcount is configured in the MCLKCtl
register must be bound between a value of 1 to 7. The possible crystal or
external clock frequencies for getting MCLK = 96MHz are shown in Table
11.”
In the
using timer 1.” to “If BSEL = 0, the baud rate is derived using timer 1.”
In
description: “The signals of the emulator port have weak pull-ups. Adding
resistor footprints for signals E_RST, E_TCLK and E_RXTX on the PCB is
recommended. If necessary, adding 10KΩ pull-up resistors on E_TCLK
and E_RXTX and a 3KΩ on E_RST will help the emulator operate
normally if a problem arises.”
In
In
In
SEC, TEST and VDD pins.
In
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
PGADDR
(see detailed description above).”
In
In
In
FUSECtl bit description to TRIMPCtl.
In
In
In
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,
LEDCal and LOCKCtl registers.
In
In
through USRIntCtl3 to USRIntCtl1 through USRIntCtl4.
In TCON, corrected the descriptions for TCON.2 and TCON.0.
In
reset.
Changed the register address for
Table
Section
Section
Section
Ordering
Table
Table
Section
Table
Table
Table
Table
Table
Table
Table
Table 50
Section
BRCON
1, added Equivalent Circuit references.
1, added the “Pin (44 QFN)” column.
1, added more description to the SCL, SDA, PRES, VCC, VPC,
5, changed “FLSHCRL” to “FLSHCTL”.
5, removed the PREBOOT bit description.
5, moved the TRIMPCtl bit description to FUSECtl and moved the
6, changed “PGADR” to “PGADDR”.
7, added PGADDR.
8, changed the reset value for RTCCtl from “0x81” to “0x00”.
7, removed the Mcount 7 row.
register, added “Note: the page address is shifted left by one bit
1.4, updated program security description to remove pre-boot
1.7.1, changed “Mcount is configured in the MCLKCtl register
1.7.14, removed the following from the emulator port
1.3.2, changed “FLSH_ERASE” to “ERASE” and
1.7.9, added a note about USR pins defaulting as inputs after
through
Information, removed the leaded part numbers.
description, changed “If BSEL = 1, the baud rate is derived
Table
53, changed the names of registers USRIntCtl0
ATRMsB
from FE21 to FE1F.
73S1210F Data Sheet
125