73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 48

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
Interrupt Enable 1 Register (IEN1): 0xB8  0x00
Interrupt Priority 0 Register (IP0): 0xA9  0x00
Note: The remaining bits in the IP0 register are not used for watchdog control.
Watchdog Timer Reload Register (WDTREL): 0x86  0x00
48
WDTREL.7
WDTREL.6
WDTREL.0
IEN1.7
IEN1.6
IEN1.5
IEN1.4
IEN1.3
IEN1.2
IEN1.1
IEN1.0
IP0.6
Bit
Bit
Bit
to
MSB
WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0
MSB
MSB
Symbol
SWDT
EX6
EX5
EX4
EX3
EX2
–
Symbol
–
WDREL6-0
WDTS
–
–
WDPSEL
Symbol
SWDT
WDTS
Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer.
When directly set after setting WDT, a watchdog timer refresh is performed. Bit
SWDT is reset by the hardware 12 clock cycles after it has been set.
EX6 = 0 – disable external interrupt 6.
EX5 = 0 – disable external interrupt 5.
EX4 = 0 – disable external interrupt 4.
EX3 = 0 – disable external interrupt 3.
EX2 = 0 – disable external interrupt 2.
Watchdog timer status flag. Set when the watchdog timer has expired. The
internal reset will be generated, but this bit will not be cleared by the reset.
This allows the user program to determine if the watchdog timer caused the
reset to occur and respond accordingly. Can be read and cleared by software.
Prescaler select bit. When set, the watchdog is clocked through an
additional divide-by-16 prescaler.
Seven bit reload value for the high-byte of the watchdog timer. This value is
loaded to the WDT when a refresh is triggered by a consecutive setting of
bits WDT and SWDT.
IP0.5
EX6
Table 46: The WDTREL Register
Table 44: The IEN1 Register
Table 45: The IP0 Register
IP0.4
EX5
IP0.3
EX4
Function
Function
IP0.2
EX3
Function
IP0.1
EX2
IP0.0
–
LSB
LSB
DS_1210F_001
LSB
Rev. 1.4