73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 27

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
73S1210F will go into the “OFF” state (when V
desired and the application does not need to shut down power on VDD, the ON_OFF input can be
permanently grounded which will automatically turn on VDD when power is supplied on any of the VPC,
VBAT or VBUS power supply inputs.
If power is applied to both V
source. The 73S1210F will be unconditionally “ON” when V
the 73S1210F will switchover to the VBAT input supply and remain in the “ON” state. The firmware
should assert SCPWRDN based on no activity or V
When operating from V
connecting V
Note: When the ON_OFF switch function is not needed, i.e. when the 73S1210F must be in an always-ON
state when using another supply than VBUS (V
1.7.4
The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby
mode or power down the 73S1210F into its “OFF” mode. The standby mode will stop the core, clock
subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or
disabling the clock going to the block. The Miscellaneous Control registers MISCtl0,
Master Clock Control register (MCLKCtl) provide control over the power modes. The PWRDN bit in
MISCtl0
circuitry and power applied to the VBUS input, the 73S1210F will go into either standby mode or power
“OFF” mode. If system power is provided by, VBUS or the ON/OFF circuitry is in the “ON” state, the MPU
core will placed into standby mode. If the VBUS input is not sourcing power and the ON/OFF circuitry is
in the “OFF” state, setting the PWRDN bit will shut down the converter and VP will turn off. The power
down mode should only be initiated by setting the PWRDN bit in the
manipulating individual control bits in various registers. Figure 6 shows how the PWRDN bit controls the
various functions that comprise power down state.
Rev. 1.4
Note: the PWRDN Signal is not the direct version of the PWRDN Bit. There are delays from assertion of the PWRDN
bit to the assertion of the PWRDN Signal (32 MPU clocks). Refer to the Power Down sequence diagram.
Power Control Modes
will setup the 73S1210F for standby or “OFF” modes. Depending on the state of the ON/OFF
BUS
to V
the names of the control bits.
These are the registers and
P
SCVCCCtl - SCPRDN
MCLCKCtl - HOSEN
VDDFCtl - VDDFEN
in order to save power.
MISCtl0 - PWRDN
ACOMP - CMPEN
MISCtl1 - FRPEN
BUS
, and not calling for V
BAT
and V
Figure 6: Power Down Control
BUS
, the circuit will automatically consume power from only the V
PWRDN Signal
BUS
PC
CC
, the step-up converter becomes a simple switch
or V
is not present). If the ON/OFF switch function is not
BUS
BAT
removal to reduce battery power consumption.
), some external discrete components are needed.
BUS
+
+
+
+
+
is applied. If the V
MISCtl0
register and not by
reference and bias
Smart Card Power
These are the block
Analog functions
Flash Read Pulse
High Speed OSC
one-shot circuit
circuits, etc.)
(VCO, PLL,
VDDFAULT
COMPARE
references.
BUS
ANALOG
73S1210F Data Sheet
MISCtl1
source is removed,
and the
BUS
27