73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 94

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
Parity Control Register (SParCtl): 0xFE11  0x00
This register provides the ability to configure the parity circuitry on the smart card interface. The settings
apply to both integrated smart card interfaces.
94
SParCtl.7
SParCtl.6
SParCtl.5
SParCtl.4
SParCtl.3
SParCtl.2
SParCtl.1
SParCtl.0
Bit
MSB
–
BRKGEN
RETRAN
FORCPE
BRKDET
DISCRX
DISPAR
Symbol
INSPE
DISPAR BRKGEN BRKDET RETRAN DISCRX
–
Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UART will
check for even parity (the number of 1’s including the parity bit is even) on
every character. This also applies to the TS during ATR.
Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will generate a Break to the smart card if a parity error is
detected on a receive character. No Break will be generated if parity
checking is disabled. This also applies to TS during ATR.
Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will detect the generation of a Break by the smart card.
Retransmit Byte – 1 = enabled, 0 = disabled. If enabled and a Break is
detected from the smart card (Break Detection must be enabled), the last
character will be transmitted again. This bit applies to T=0 protocol.
Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity
error is detected (Parity checking must be enabled), the last character
received will be discarded. This bit applies to T=0 protocol.
Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
enabled, the UART will insert a parity error in every character transmitted by
generating odd parity instead of even parity for the character.
Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
enabled, the UART will generate a parity error on a character received from
the smart card.
Table 88: The SParCtl Register
Function
INSPE
FORCPE
DS_1210F_001
LSB
Rev. 1.4