73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 92

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
Protocol Mode Register (SPrtcol): 0xFE0D  0x03
This register determines the protocol to be use when communicating with the selected smart card. This
register should be updated as required when switching between smart card interfaces.
92
SPrtcol.7
SPrtcol.6
SPrtcol.5
SPrtcol.4
SPrtcol.3
SPrtcol.2
SPrtcol.1
SPrtcol.0
Bit
MSB
SCISYN
MOD9/8B
SCESYN
RCVATR
SCISYN
CRCMS
Symbol
TMODE
CRCEN
MOD9/8B SCESYN
0
Smart Card Internal Synchronous mode - Configures internal smart card
interface for synchronous mode. This mode routes the internal interface
buffers for RST, IO, C4, C8 to the
control. CLK is generated by the ETU counter.
Synchronous 8/9 bit mode select - For sync mode, in protocols with 9-bit
words, set this bit. The first eight bits read go into the RX FIFO and the
ninth bit read will be stored in the IO (or SIO) data bit of the
Smart Card External Synchronous mode - Configures External Smart Card
interface for synchronous mode. This mode routes the external smart card
interface buffers for SIO to
SCLK is generated by the ETU counter.
Reserved bit, must always be set to 0.
Protocol mode select - 0: T=0, 1: T=1. Determines which smart card
protocol is to be used during message processing.
CRC Enable – 1 = Enabled, 0 = Disabled. Enables the checking/generation
of CRC/LRC while in T=1 mode. Has no effect in T=0 mode. If enabled and
a message is being transmitted to the smart card, the CRC/LRC will be
inserted into the message stream after the last TX byte is transmitted to the
smart card. If enabled, CRC/LRC will be checked on incoming messages
and the value made available to the firmware via the CRC LS/MS registers.
CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking
algorithm to be used.
Receive ATR – 1 = Enable ATR timeout, 0 = Disable ATR timeout. Set by
firmware after the smart card has been turned on and the hardware is
expecting ATR.
Table 85: The SPrtcol Register
0
TMODE
SCECtl
Function
SCCtl
register bits for direct firmware control.
CRCEN
register bits for direct firmware
CRCMS
RCVATR
SRXCtl
DS_1210F_001
LSB
register.
Rev. 1.4