73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 93

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS_1210F_001
SC Clock Configuration Register (SCCLK): 0xFE0F  0x0C
This register controls the internal smart card (CLK) clock generation.
External SC Clock Configuration Register (SCECLK): 0xFE10  0x0C
This register controls the external smart card (SCLK) clock generation.
MSB
Rev. 1.4
SCECLK.7
SCECLK.6
SCECLK.5
SCECLK.4
SCECLK.3
SCECLK.2
SCECLK.1
SCECLK.0
SCCLK.7
SCCLK.6
SCCLK.5
SCCLK.4
SCCLK.3
SCCLK.2
SCCLK.1
SCCLK.0
MSB
–
Bit
Bit
–
ECLKFS.5
ECLKFS.4
ECLKFS.3
ECLKFS.2
ECLKFS.1
ECLKFS.0
ICLKFS.5
ICLKFS.4
ICLKFS.3
ICLKFS.2
ICLKFS.1
ICLKFS.0
Symbol
Symbol
–
–
–
–
–
–
ECLKFS.5
ICLKFS.5 ICLKFS.4 ICLKFS.3 ICLKFS.2 ICLKFS.1 ICLKFS.0
Internal Smart Card CLK Frequency Select - Division factor to determine
internal smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate CLK.
Default ratio is 13. The programmed value in this register is applied to the
divider after this value is written, in such a manner as to produce a
glitch-free output, regardless of the selection of active interface. A
register value = 0 will default to the same effect as register value = 1.
External Smart Card CLK Frequency Select - Division factor to determine
external smart card CLK frequency. MCLK clock is divided by (register
value + 1) to clock the ETU divider, and then by 2 to generate SCLK.
Default ratio is 13. The programmed value in this register is applied to the
divider after this value is written, in such a manner as to produce a
glitch-free output, regardless of the selection of active interface. A
register value = 0 will default to the same effect as register value = 1.
Table 87: The SCECLK Register
Table 86: The SCCLK Register
ECLKFS.4
ECLKFS.3
Function
Function
ECLKFS.2
ECLKFS.1
73S1210F Data Sheet
ECLKFS.0
LSB
LSB
93