73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 38

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
1.7.5.4
The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down
(CPU STOP) state. See the
1.7.5.5
All interrupt sources are combined in groups, as shown in Table 27.
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or
clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level
are received simultaneously, an internal polling sequence as per
serviced first.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler.
Interrupt Priority 0 Register (IP0): 0xA9  0x00
Note: WDTS is not used for interrupt controls.
38
Enable Bit
EX0
EX1
EX2
EX3
EX4
EX5
EX6
Group
Power Down Interrupt Logic
Interrupt Priority Level Structure
0
1
2
3
4
5
MSB
–
Description
Enable external interrupt 0
Enable external interrupt 1
Enable external interrupt 2
Enable external interrupt 3
Enable external interrupt 4
Enable external interrupt 5
Enable external interrupt 6
Serial channel 0 interrupt
External interrupt 0
External interrupt 1
Timer 0 interrupt
Timer 1 interrupt
WDTS
Power Control Modes
Table 26: Control Bits for External Interrupts
–
IP0.5
Table 27: Priority Level Groups
Table 28: The IP0 Register
IP0.4
Serial channel 1 interrupt
section for details.
IP0.3
Flag Bit
IEX2
IEX3
IEX4
IEX5
IEX6
IE0
IE1
–
–
–
–
–
IP0.2
Table 31
Description
External interrupt 0 flag
External interrupt 1 flag
External interrupt 2 flag
External interrupt 3 flag
External interrupt 4 flag
External interrupt 5 flag
External interrupt 6 flag
IP0.1
determines which request is
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
IP0.0
LSB
DS_1210F_001
Rev. 1.4