73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 40

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
1.7.6
The 80515 core of the 73S1210F includes two separate UARTs that can be programmed to communicate
with a host. The 73S1210F can only connect one UART at a time since there is only one set of TX and
Rx pins. The
UART has a different set of operating modes that the user can select according to their needs. The
UART is a dedicated 2-wire serial interface, which can communicate with an external host processor at
up to 115,200 bits/s. The TX and RX pins operate at the V
exceed 3.6V. The operation of each pin is as follows:
RX: Serial input data is applied at this pin. Conforming to RS-232 standard, the bytes are input LSB first.
The voltage applied at RX must not exceed 3.6V.
TX: This pin is used to output the serial data. The bytes are output LSB first.
The 73S1210F has several UART-related read/write registers. All UART transfers are programmable for
parity enable, parity select, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud
rates from 300 to 115200 bps.
shows how the baud rates are calculated.
Note: Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes with
parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of 8-bit
output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a constant 1. 8-bit
serial modes with parity can be simulated by setting and reading the 9th bit, using the control bits
S0CON3 and S1CON3 in the S0COn and S1CON SFRs.
Note: S0REL (9:0) and S1REL (9:0) are 10-bit values derived by combining bits from the respective timer
reload registers SxRELH (bits 1:0) and SxRELL (bits 7:0). TH1 is the high byte of timer 1. The SMOD bit
is located in the
40
Serial Interface 0
Serial Interface 1
Mode 0
Mode 1
Mode 2
Mode 3
UART
MISCtl0
Start bit, 8 data bits, parity, stop bit, fixed
baud rate (internal baud rate generator
PCON
Start bit, 8 data bits, stop bit, variable
variable baud rate (internal baud rate
Start bit, 8 data bits, parity, stop bit,
baud rate 1/32 or 1/64 of f
register is used to select which UART is connected to the TX and RX pins. Each
2
SFR.
generator or timer 1).
smod
* f
or timer 1).
CKMPU
UART 0
Table 33
Using Timer 1
N/A
Table 34: Baud Rate Generation
/ (384 * (256-TH1))
N/A
Table 33: UART Modes
shows the selectable UART operation modes and
CKMPU.
Start bit, 8 data bits, parity, stop bit, variable
DD
Start bit, 8 data bits, stop bit, variable baud
baud rate (internal baud rate generator).
Using Internal Baud Rate Generator
supply voltage levels and should never
rate (internal baud rate generator).
2
smod
f
CKMPU
* f
CKMPU
/(32 * (2
UART 1
/(64 * (2
N/A
N/A
10
-S1REL))
10
-S0REL))
DS_1210F_001
Table 34
Rev. 1.4