73S1210F-68IM/F Maxim Integrated Products, 73S1210F-68IM/F Datasheet - Page 62

• Manufacturer Part Number: 73S1210F-68IM/F
• Description: IC SMART CARD READER 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73S1210F-68IM/F

• Core Processor: 80515
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, SmartCard, UART/USART
• Peripherals: LED, POR, WDT
• Number Of I /o: 8
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

73S1210F Data Sheet
written into the
12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the
and Clock Generation
within the
Normal scanning is performed by hardware when the SCNEN bit is set at 1 in the
13
does not occur until a key-press is detected. Once hardware key scanning is enabled, the hardware
drives all column outputs low and waits for a low to be detected on one of the inputs. When a low is
detected on any row, and before key scanning starts, the hardware checks that the low level is still
detected after a debounce time. The debounce time is defined by firmware in the
7:0, DBTIME). Debounce times from 4ms to 256ms in 4ms increments are supported. If a key is not
pressed after the debounce time, the hardware will go back to looking for any input to be low. If a key is
confirmed to be pressed, key scanning begins.
Key scanning asserts one of the 5 drive lines (COL 4:0) low and looks for a low on a sense line indicating
that a key is pressed at the intersection of the drive/sense line in the keypad. After all sense lines have
been checked without a key-press being detected, the next column line is asserted. The time between
checking each sense line is the scan time and is defined by firmware in the
SCTIME). Scan times from 1ms to 4ms are supported. Scanning order does not affect the scan time.
This scanning continues until the entire keypad is scanned. If only one key is pressed, a valid key is
detected. Simultaneous key presses are not considered as valid (If two keys are pressed, no key is
reported to firmware).
Possible scrambling of the column scan order is provided by means of the
registers that define the order of column scanning. Values in these registers must be updated every time
a new keyboard scan order is desired. It is not possible to change the order of scanning the sense lines.
The column and row intersection for the detected valid key are stored in the
When a valid key is detected, an interrupt is generated. Firmware can then read those registers to
determine which key had been pressed. After reading the
update the
enabled in the KSTAT register, the
been identified. The hardware does not wait for the firmware to service the interrupt in order to proceed
with the key scanning process. Once the valid key (or invalid key – e.g. two keys pressed) is detected,
the hardware waits for the key to be released. Once the key is released, the debounce timer is started. If
the key is not still released after the debounce time, the debounce counter starts again. After a key
release, all columns will be driven low as before and the process will repeat waiting for any key to be
pressed. When the SCNEN bit is disabled, all drive outputs are set to the value in the
firmware clears the SCNEN bit in the middle of a key scan, the
stored in there which will then be reflected on the output pins. A bypass mode is provided so that the
firmware can do the key scanning manually (SCNEN bit must be cleared). In bypass mode, the firmware
writes/reads the Column and Row registers to perform the key scanning.
62
shows the flowchart of how the hardware scanning operates. In order to minimize power, scanning
KSIZE
KORDERL
KCOL
register.
and
section) to carry out scanning and debouncing. The keypad size can be adjusted
/
KORDERH
KROW
registers. The keypad interface uses a 1kHz clock derived from the
KCOL
registers if a new scan order is needed. When the SCNEN bit is
and
KROW
registers are only updated after a valid key has
KCOL
KCOL
and
MCLKCtl
KROW
register contains the last value
KORDERL
KSCAN
KCOL
registers, the firmware can
register (see the
KSTAT
KSCAN
and
register (bits 0:1 –
and
KCOL
KROW
register.
DS_1210F_001
register (bits
KORDERH
register. If
registers.
Oscillator
Rev. 1.4
Figure